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TC9WMC2FU Scheda tecnica(PDF) 8 Page - Toshiba Semiconductor |
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TC9WMC2FU Scheda tecnica(HTML) 8 Page - Toshiba Semiconductor |
8 / 16 page TC9WMC1FK/FU,TC9WMC2FK/FU 2007-10-19 8 (3.5) Erase All (ERASE) The Erase All instruction writes every bit in the memory array to 1. After the CS is driven High, a start bit is transferred followed by the ERAL instruction and any addresses. In this mode, data does not need to be transferred. After the least significant bit (A0) of the address is received on the falling edge of SK, an erase operation is triggered by the CS being pulled Low. CS SK 1 2 7 8 9 1 0 0 DI DO Hi-Z 1 3 4 5 6 0 x x x x Hi-Z Figure 9. Erase Timing Diagram (TC9WMC1) Busy Ready Verify tPW CS SK 1 2 7 8 9 10 1 0 0 DI DO Hi-Z x 3 4 5 6 x x x x x Hi-Z Figure 10. Erase Timing Diagram (TC9WMC2) Busy Ready Verify 11 0 1 tPW |
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