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DM74LS163A Scheda tecnica(PDF) 3 Page - Fairchild Semiconductor

Il numero della parte DM74LS163A
Spiegazioni elettronici  Synchronous 4-Bit Binary Counters
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Produttore elettronici  FAIRCHILD [Fairchild Semiconductor]
Homepage  http://www.fairchildsemi.com
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DM74LS163A Scheda tecnica(HTML) 3 Page - Fairchild Semiconductor

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’LS161 Electrical Characteristics (Continued)
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 4)
I
I
Input Current @ Max
V
CC = Max
Enable T
0.2
Input Voltage
V
I = 7V
Clock
0.2
mA
Load
0.2
Others
0.1
I
IH
High Level Input
V
CC = Max
Enable T
40
Current
V
I = 2.7V
Clock
40
µA
Load
40
Others
20
I
IL
Low Level Input
V
CC = Max
Enable T
−0.8
Current
V
I = 0.4V
Clock
−0.8
mA
Load
−0.8
Others
−0.4
I
OS
Short Circuit
V
CC = Max
DM54
−20
−100
mA
Output Current
(Note 5)
DM74
−20
−100
I
CCH
Supply Current with
V
CC = Max
18
31
mA
Outputs High
(Note 6)
I
CCL
Supply Current with
V
CC = Max
19
32
mA
Outputs Low
(Note 7)
Note 4: All typicals are at VCC = 5V, TA = 25˚C.
Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 6: ICCH is measured with the load high, then again with the load low, with all other inputs high and all outputs open.
Note 7: ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
’LS161 Switching Characteristics
at V
CC = 5V and TA = 25˚C
From (Input)
R
L = 2kΩ
Symbol
Parameter
To (Output)
C
L = 15 pF
C
L = 50 pF
Units
Min
Max
Min
Max
f
MAX
Maximum Clock Frequency
25
20
MHz
t
PLH
Propagation Delay Time
Clock to
25
30
ns
Low to High Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Clock to
30
38
ns
High to Low Level Output
Ripple Carry
t
PLH
Propagation Delay Time
Clock to Any Q
22
27
ns
Low to High Level Output
(Load High)
t
PHL
Propagation Delay Time
Clock to Any Q
27
38
ns
High to Low Level Output
(Load High)
t
PLH
Propagation Delay Time
Clock to Any Q
24
30
ns
Low to High Level Output
(Load Low)
t
PHL
Propagation Delay Time
Clock to Any Q
27
38
ns
High to Low Level Output
(Load Low)
t
PLH
Propagation Delay Time
Enable T to
14
27
ns
Low to High Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Enable T to
15
27
ns
High to Low Level Output
Ripple Carry
t
PHL
Propagation Delay Time
Clear to
28
45
ns
High to Low Level Output
Any Q
3
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