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TMP86FM48 Scheda tecnica(PDF) 4 Page - Toshiba Semiconductor |
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TMP86FM48 Scheda tecnica(HTML) 4 Page - Toshiba Semiconductor |
4 / 205 page TMP86FM48 2007-08-24 86FM48-2 ♦ Serial interface • UART/SIO: 1ch • SIO: 1ch • I2C bus: 1ch ♦ 10-bit successive approximation type AD converter • Analog input: 16 ch ♦ Four Key-on wake-up pins ♦ Dual clock operation • Single/dual-clock mode ♦ Nine power saving operating modes • STOP mode: Oscillation stops. Battery/capacitor back-up. Port output hold/High-impedance. • SLOW 1, 2 mode: Low-power consumption operation using low-frequency clock (32.768 kHz) • IDLE 0 mode: CPU stops, and peripherals operate using high-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR <TBTCK> setting. • IDLE 1 mode: CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. • IDLE 2 mode: CPU stops, and peripherals operate using high and low-frequency clock. Release by interruputs. • SLEEP 0 mode: CPU stops, and peripherals operate using low-frequency clock of time-base-timer. Release by falling edge of TBTCR <TBTCK> setting. • SLEEP 1 mode: CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. • SLEEP 2 mode: CPU stops, and peripherals operate using high- and low-frequency clock. Release by interrupts. ♦ Wide operating voltage: 1.8 to 3.6 V at 8 MHz/32.768 kHz 2.7 to 3.6 V at 16 MHz/32.768 kHz |
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