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SI3460 Scheda tecnica(PDF) 9 Page - Silicon Laboratories |
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SI3460 Scheda tecnica(HTML) 9 Page - Silicon Laboratories |
9 / 22 page Si3460 Preliminary Rev. 0.4 9 4.1. PSE Timing Characteristics When implemented in accordance with the recommended external components and layout guidelines, the Si3460 controller enables the following typical performance characteristics in single-port PSE applications. Refer to the Si3460-EVB applications note, schematics, and user's guide for more details. 4.1.1. PSE Timing Diagrams The basic sequence of applying power is shown in Figure 3. Following is the description of the function that must be performed in each phase. Figure 3. Detection, Classification, Powerup, and Disconnect Sequence Table 6. PSE Timing* Description Symbol Test Conditions Min Typ Max Unit Endpoint detection delay cycle tDET_CYCLE Time from PD connection to port to completion of detection process. 70 400 ms Detection time tDETECT Time required to measure PD sig- nature resistance. 70 ms Classification delay cycle tCLASS_CYCLE Time from successful detect mode to classification complete. 10 50 ms Classification time tCLASS 10 50 ms Power-up turn-on delay tPWRUP Time from when a valid detection is completed until VOUT power is applied 30 ms Midspan detect backoff time tBOM 2s Current limit time tLIM 60 ms Disconnect delay tDC_DIS 350 ms *Note: These typical specifications are based on an ambient operating temperature of 25 ºC and VIN =+12 V. tDET_CYCLE Time (msec) 2.8 V 10 V 15.5 V 44 V 57 V 20.5 V tCLASS_CYCLE tPWRUP |
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