All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2006 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

VHDL Source Code or/and

DELIVERABLES

Source code:

VERILOG Source Code or/and

Encrypted, or plain text EDIF

VHDL & VERILOG test bench environment

Active-HDL automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor and

major versions changes

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Delivery the documentation updates

Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow use

IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restriction

except One Year license where time of use is

limited to 12 months.

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Single Design license for

VHDL, Verilog source code called HDL Source

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Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

PINS DESCRIPTI O N

PIN

ACTIVE

TYPE

DESCRIPTION

clk

-

input

Global system clock

rst

Low

input

Global reset input

int

Low

input

Interrupt request

nmi

Low

input

Non-Maskable Interrupt Request

wait

Low

input

WAIT input

busreq

Low

input

Bus Request

datai[7:0]

-

input

Memory bus input

datao[7:0]

-

output

Data memory & UFR bus output

addr[15:0]

-

output

Data memory address bus

wr

Low

output

Write enable

rd

Low

output

Read enable

busack

Low

output

Bus Acknowledge

m1

Low

output

Machine Cycle One

mreq

Low

output

Memory Request

iorq

Low

output

Input/Output Request

rfsh

Low

output

Refresh

halt

Low

output

Halt State

SYMBOL

addr(15:0)

wr

rd

datai(7:0)

int

nmi

busrq

wait

clk

datao(7:0)

halt

rst

m1

mreq

iorq

rfsh

busack

BLOCK DIAGRAM

Control Unit

- Performs the core synchroniza-

tion and data flow control. This module man-

ages execution of all instructions. The Control

Unit also manages execution of HALT state and

waking-up the processor from the HALT mode.

Opcode Decoder

- Performs an instruction

opcode decoding and the control functions for

all other blocks.