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DAC5682ZIRGCR Scheda tecnica(PDF) 9 Page - Texas Instruments |
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DAC5682ZIRGCR Scheda tecnica(HTML) 9 Page - Texas Instruments |
9 / 56 page www.ti.com ELECTRICAL CHARACTERISTICS (DIGITAL SPECIFICATIONS) DAC5682Z SLLS853A – AUGUST 2007 – REVISED NOVEMBER 2007 over recommended operating free-air temperature range, AVDD, IOVDD = 3.3V, CLKVDD, DVDD = 1.8V. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT LVDS INTERFACE: D[15:0]P, D[15:0]N, SYNCP/N, DCLKP/N Positive-going 175 VITH+ differential input mV voltage threshold Negative-going –175 VITH– differential input mV voltage threshold Input Common SYNCP/N, D[15:0]P and D[15:0]N only 1.2 VCOM1 V Mode Input Common DCLKP/N only DVDD/ VCOM2 V Mode 2 ZT Internal termination SYNCP/N, D[15:0]P and D[15:0]N only 100 110 120 Ω LVDS Input CL 2 pF capacitance DCLKP/N: 0 to 125MHz (see Figure 33) Setup_min 1100 tS, tH DCLK to Data CONFIG5 DLL_bypass = 1, CONFIG10 = '00000000' Hold_min –600 DCLKP/N = 150MHz Positive 1000 CONFIG5 DLL_bypass = 0, Negative –1800 DCLKP/N = 200MHz Positive 800 CONFIG5 DLL_bypass = 0 Negative –1300 DCLKP/N = 250MHz Positive 600 CONFIG5 DLL_bypass = 0 Negative –1000 DCLK to Data DCLKP/N = 300MHz Positive 450 Skew(1) CONFIG5 DLL_bypass = 0 ps Negative –800 tSKEW(A), [Please contact DCLKP/N = 350 MHz Positive 400 tSKEW(B) factory for CONFIG5 DLL_bypass = 0 recommended DLL Negative –700 settings] DCLKP/N = 400 MHz CONFIG5 DLL_bypass = 0 Positive 300 Refer to supported data rate [fDATA ] Negative –600 DCLKP/N = 450 MHz CONFIG5 DLL_bypass = 0 Positive 300 Refer to supported data rate [fDATA ] Negative –500 DCLKP/N = 500 MHz, T = 25 °C to 85 °C CONFIG5 Positive 350 DLL_bypass = 0 Negative –300 Refer to supported data rate [fDATA ] DLL Enabled, T = 25 °C to 85 °C 250 1000 DDR format, DCLKP frequency: 125 to 500 MHz Input data rate DLL Enabled, T = –40 °C fDATA 250 750 MSPS supported DDR format, DCLK frequency: 125 to 375 MHz DLL Disabled, T = –40 °C to 85 °C 250 DDR format, DCLKP frequency: <125 MHz CMOS INTERFACE: SDO, SDIO, SCLK, SDENB, RESETB High-level input 2 3 VIH V voltage Low-level input 0 0 0.8 VIL V voltage High-level input –40 40 IIH µA current Low-level input –40 40 IIL µA current CMOS Input 5 CI pF capacitance (1) Positive skew: Clock ahead of data. Negative skew: Data ahead of clock. Copyright © 2007, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): DAC5682Z |
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