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74AUP1G00 Scheda tecnica(PDF) 9 Page - NXP Semiconductors |
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74AUP1G00 Scheda tecnica(HTML) 9 Page - NXP Semiconductors |
9 / 16 page 74AUP1G00_2 © Koninklijke Philips Electronics N.V. 2006. All rights reserved. Product data sheet Rev. 02 — 29 June 2006 9 of 16 Philips Semiconductors 74AUP1G00 Low-power 2-input NAND gate 12. Waveforms CL = 15 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 3.1 16.5 3.1 18.2 ns VCC = 1.4 V to 1.6 V 2.5 10.5 2.5 11.6 ns VCC = 1.65 V to 1.95 V 2.0 8.3 2.0 9.2 ns VCC = 2.3 V to 2.7 V 1.5 6.4 1.5 7.1 ns VCC = 3.0 V to 3.6 V 1.4 5.7 1.4 6.3 ns CL = 30 pF tPHL, tPLH HIGH-to-LOW and LOW-to-HIGH propagation delay A or B to Y see Figure 7 VCC = 1.1 V to 1.3 V 4.1 22.6 4.1 24.9 ns VCC = 1.4 V to 1.6 V 2.9 14.0 2.9 15.4 ns VCC = 1.65 V to 1.95 V 2.3 11.1 2.3 12.3 ns VCC = 2.3 V to 2.7 V 2.1 8.5 2.1 9.4 ns VCC = 3.0 V to 3.6 V 2.1 7.6 2.1 8.4 ns Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8 Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Max Min Max Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load. Fig 7. The data input (A or B) to output (Y) propagation delays mna612 tPHL tPLH VM VM A, B input Y output GND VI VOH VOL Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 0.8 V to 3.6 V 0.5 × VCC 0.5 × VCC VCC ≤ 3.0 ns |
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