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74LVCH322245AEC Scheda tecnica(PDF) 1 Page - NXP Semiconductors |
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74LVCH322245AEC Scheda tecnica(HTML) 1 Page - NXP Semiconductors |
1 / 13 page 1. General description The 74LVCH322245A is a 32-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The device features four output enable (nOE) inputs for easy cascading and four send/receive (nDIR) inputs for direction control. Pin nOE controls the outputs so that the buses are effectively isolated. The device is designed with 30 Ω series termination resistors in both HIGH and LOW output stages to reduce line noise. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. To ensure the high-impedance state during power-up or power-down, pin nOE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs. 2. Features I 5 V tolerant inputs/outputs for interfacing with 5 V logic I Wide supply voltage range from 1.2 V to 3.6 V I CMOS low power consumption I MULTIBYTE flow-through standard pin-out architecture I Low inductance multiple power and ground pins for minimum noise and ground bounce I Direct interface with TTL levels I Inputs accept voltages up to 5.5 V I All data inputs have bus hold I Integrated 30 Ω termination resistors I Complies with JEDEC standard JESD8-B / JESD36 I ESD protection: N HBM EIA/JESD22-A114-B exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V I Specified from −40 °Cto+85 °C I Packaged in plastic fine-pitch ball grid array package 74LVCH322245A 32-bit bus transceiver with direction pin; 30 Ω series temination resistors; 5 V tolerant; 3-state Rev. 03 — 20 August 2007 Product data sheet |
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