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74LVC2G125GT Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74LVC2G125GT Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 16 page 74LVC2G125_8 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 08 — 7 September 2007 3 of 16 NXP Semiconductors 74LVC2G125 Dual bus buffer/line driver; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description Fig 3. Pin configuration TSSOP8 and VSSOP8 1OE VCC 1A 2OE 2Y 1Y GND 2A 001aab738 1 2 3 4 6 5 8 7 74LVC2G125 Fig 4. Pin configuration XSON8 Fig 5. Pin configuration XQFN8 74LVC2G125 1Y 2OE VCC 2A 2Y 1A 1OE GND 001aab739 36 27 18 45 Transparent top view 001aae010 1A 1Y 1OE 2Y 2OE 2A Transparent top view 3 6 1 5 7 2 terminal 1 index area 74LVC2G125 Table 3: Pin description Symbol Pin Description TSSOP8; VSSOP8 XSON8 XQFN8 1OE 1 1 7 output enable input (active LOW) 1A 2 2 6 data input 2Y 3 3 5 data output GND 4 4 4 ground (0 V) 2A 5 5 3 data input 1Y 6 6 2 data output 2OE 7 7 1 output enable input (active LOW) VCC 8 8 8 supply voltage |
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