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74LVC2G74GM Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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74LVC2G74GM Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
8 / 19 page 74LVC2G74_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 9 August 2007 8 of 19 NXP Semiconductors 74LVC2G74 Single D-type flip-flop with set and reset; positive edge trigger 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 9. Symbol Parameter Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max tpd propagation delay CP to Q, Q; see Figure 7 [2] VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 1.5 13.4 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 2.7 V 1.0 3.5 7.1 1.0 7.1 ns VCC = 3.0 V to 3.6 V 1.0 3.5 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns SD to Q, Q; see Figure 8 [2] VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns RD to Q, Q; see Figure 8 [2] VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 1.5 12.9 ns VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns tW pulse width CP HIGH or LOW; see Figure 7 VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns SD and RD LOW; see Figure 8 VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns VCC = 2.7 V 2.7 - - 2.7 - ns VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns |
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