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74LVC2G125DP Scheda tecnica(PDF) 1 Page - NXP Semiconductors

Il numero della parte 74LVC2G125DP
Spiegazioni elettronici  Dual bus buffer/line driver; 3-state
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Produttore elettronici  NXP [NXP Semiconductors]
Homepage  http://www.nxp.com
Logo NXP - NXP Semiconductors

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1.
General description
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at
all inputs makes the circuit highly tolerant of slower input rise and fall times.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2.
Features
s Wide supply voltage range from 1.65 V to 5.5 V
s 5 V tolerant input/output for interfacing with 5 V logic
s High noise immunity
s Complies with JEDEC standard:
x JESD8-7 (1.65 V to 1.95 V)
x JESD8-5 (2.3 V to 2.7 V)
x JESD8-B/JESD36 (2.7 V to 3.6 V)
s ESD protection:
x HBM EIA/JESD22-A114E exceeds 2000 V
x MM EIA/JESD22-A115-A exceeds 200 V
s
±24 mA output drive (V
CC = 3.0 V)
s CMOS low-power consumption
s Latch-up performance exceeds 250 mA
s Direct interface with TTL levels
s Inputs accept voltages up to 5 V
s Multiple package options
s Specified from
−40 °C to +85 °C and −40 °C to +125 °C
74LVC2G125
Dual bus buffer/line driver; 3-state
Rev. 08 — 7 September 2007
Product data sheet


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