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74AUP1T97GM Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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74AUP1T97GM Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 17 page 74AUP1T97_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 25 October 2007 10 of 17 NXP Semiconductors 74AUP1T97 Low-power configurable gate with voltage-level translator 12. Waveforms Measurement points are given in Table 10. VOL and VOH are typical output voltage drop that occur with the output load. Fig 12. Input A, B and C to output Y propagation delay times. Y output A, B, C input Y output GND VI VOH VOH VOL VOL VM VM VM VM VM VM tPLH tPLH tPHL tPHL 001aab593 Table 10. Measurement points Supply voltage Output Input VCC VM VM VI tr = tf 2.3 V to 3.6 V 0.5VCC 0.5VI 1.65 V to 3.6 V ≤ 3.0 ns |
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