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74ALVC374BQ Scheda tecnica(PDF) 4 Page - NXP Semiconductors |
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74ALVC374BQ Scheda tecnica(HTML) 4 Page - NXP Semiconductors |
4 / 17 page 74ALVC374_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 17 October 2007 4 of 17 NXP Semiconductors 74ALVC374 Octal D-type flip-flop; positive-edge trigger; 3-state 5. Pinning information 5.1 Pinning 5.2 Pin description (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig 5. Pin configuration SO20 and TSSOP20 Fig 6. Pin configuration DHVQFN20 374 OE VCC Q0 Q7 D0 D7 D1 D6 Q1 Q6 Q2 Q5 D2 D5 D3 D4 Q3 Q4 GND CP 001aad040 1 2 3 4 5 6 7 8 9 10 12 11 14 13 16 15 18 17 20 19 001aad088 374 GND(1) Transparent top view Q4 D3 Q3 D4 D2 D5 Q2 Q5 Q1 Q6 D1 D6 D0 D7 Q0 Q7 9 12 8 13 7 14 6 15 5 16 4 17 3 18 2 19 terminal 1 index area Table 2. Pin description Symbol Pin Description D[0:7] 3, 4, 7, 8, 13, 14, 17, 18 data input CP 11 clock input (LOW to HIGH, edge-triggered) OE 1 output enable input (active LOW) Q[0:7] 2, 5, 6, 9, 12, 15, 16, 19 3-state flip-flop output VCC 20 supply voltage GND 10 ground (0 V) |
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