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KMA199E Scheda tecnica(PDF) 10 Page - NXP Semiconductors |
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KMA199E Scheda tecnica(HTML) 10 Page - NXP Semiconductors |
10 / 31 page KMA199E_1 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 01 — 18 October 2007 10 of 31 NXP Semiconductors KMA199E Programmable angle sensor [1] At a nominal output voltage between 5 %VDD and 95 %VDD and a maximum angle of αmax = 180°. [2] In steps of resolution < 0.022 °. [3] Activation is dependent on the programmed diagnostic mode. [4] In steps of 0.02 %VDD. [5] At a low-pass filtered analog output with a cut-off frequency of 0.7 kHz. [6] See Section 12. [7] Temperature range −40 °C to +140 °C. [8] Based on a 3 σ standard deviation. ∆φ hys hysteresis error referred to input [5][6] - - 0.09 deg ∆φµlin microlinearity error referred to input [5][6] −0.1 - +0.1 deg ZO(pl) power-lost output impedance impedance to remaining supply line in case of lost supply voltage or lost ground - - 210 Ω Table 11. System performance …continued Characteristics are valid for the operating conditions, as specified in Section 9. Symbol Parameter Conditions Min Typ Max Unit Table 12. Dynamics Characteristics are valid for the operating conditions, as specified in Section 9. Symbol Parameter Conditions Min Typ Max Unit ton turn-on time until first valid result - - 5 ms fupd update frequency 2 3.125 - kHz ts settling time after an ideal mechanical angle step of 45 °, until 90 % of the final value is reached; CL =5nF - - 1.8 ms tcmd(ent) enter command mode time after power on 16 - 26 ms Table 13. Digital interface Characteristics are valid for the operating conditions, as specified in Section 9. Symbol Parameter Conditions Min Typ Max Unit VIH HIGH-level input voltage 80 - - %VDD VIL LOW-level input voltage - - 20 %VDD VOH HIGH-level output voltage IO =2mA 80 - - %VDD VOL LOW-level output voltage IO =2mA - - 20 %VDD Iod overdrive current absolute value for overdriving the output buffer - - 20 mA tstart start time LOW level before rising edge 5 - - µs tstop stop time HIGH level before falling edge 5 - - µs Tbit bit period minimum period may be limited by the load capacitance 10 - 100 µs tw0 pulse width 0 0.175Tbit 0.25Tbit 0.375Tbit s tw1 pulse width 1 0.625Tbit 0.75Tbit 0.825Tbit s tto time-out time digital communication reset guaranteed after maximum tto - - 220 µs |
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