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ADF4157BCPZ-RL1 Scheda tecnica(PDF) 4 Page - Analog Devices |
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ADF4157BCPZ-RL1 Scheda tecnica(HTML) 4 Page - Analog Devices |
4 / 20 page ADF4157 Rev. 0 | Page 4 of 20 TIMING SPECIFICATIONS AVDD = DVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 20 ns min LE setup time t2 10 ns min DATA to CLOCK setup time t3 10 ns min DATA to CLOCK hold time t4 25 ns min CLOCK high duration t5 25 ns min CLOCK low duration t6 10 ns min CLOCK to LE setup time t7 20 ns min LE pulse width CLK DATA LE LE DB23 (MSB) DB22 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t7 t6 t4 t5 Figure 2. Timing Diagram |
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