Motore di ricerca datesheet componenti elettronici
  Italian  ▼
ALLDATASHEETIT.COM

X  

FM25L512 Scheda tecnica(PDF) 7 Page - Ramtron International Corporation

Il numero della parte FM25L512
Spiegazioni elettronici  512Kb FRAM Serial 3V Memory
Download  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Produttore elettronici  RAMTRON [Ramtron International Corporation]
Homepage  http://www.ramtron.com
Logo RAMTRON - Ramtron International Corporation

FM25L512 Scheda tecnica(HTML) 7 Page - Ramtron International Corporation

Back Button FM25L512 Datasheet HTML 3Page - Ramtron International Corporation FM25L512 Datasheet HTML 4Page - Ramtron International Corporation FM25L512 Datasheet HTML 5Page - Ramtron International Corporation FM25L512 Datasheet HTML 6Page - Ramtron International Corporation FM25L512 Datasheet HTML 7Page - Ramtron International Corporation FM25L512 Datasheet HTML 8Page - Ramtron International Corporation FM25L512 Datasheet HTML 9Page - Ramtron International Corporation FM25L512 Datasheet HTML 10Page - Ramtron International Corporation FM25L512 Datasheet HTML 11Page - Ramtron International Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 13 page
background image
FM25L512
Rev. 1.2
Aug. 2007
Page 7 of 13
Bits 0, 4, 5 are fixed at 0 and bit 6 is fixed at 1, and
none of these bits can be modified. Note that bit 0
(“Ready” in EEPROMs) is unnecessary as the FRAM
writes in real-time and is never busy, so it reads out
as a ‘0’. The BP1 and BP0 control software write
protection features. They are nonvolatile (shaded
yellow). The WEL flag indicates the state of the
Write Enable Latch. Attempting to directly write the
WEL bit in the Status Register has no effect on its
state. This bit is internally set and cleared via the
WREN and WRDI commands, respectively.
BP1 and BP0 are memory block write protection bits.
They specify portions of memory that are write-
protected as shown in the following table.
Table 3. Block Memory Write Protection
BP1
BP0
Protected Address Range
0
0
None
0
1
C000h to FFFFh (upper ¼)
1
0
8000h to FFFFh (upper ½)
1
1
0000h to FFFFh (all)
The BP1 and BP0 bits and the Write Enable Latch
are the only mechanisms that protect the memory
from writes. The remaining write protection features
protect inadvertent changes to the block protect bits.
The WPEN bit controls the effect of the hardware pin
/WP. When WPEN=0, the /WP pin is ignored. When
WPEN=1, the /WP pin controls write access to the
Status Register. Thus the Status Register is write-
protected only when WPEN=1 and the /WP pin is
low.
This scheme provides a write protection mechanism,
which can prevent software from writing the memory
under any circumstances. This occurs if the BP1 and
BP0 are set to 1, the WPEN bit is set to 1, and the
/WP pin is low.
This occurs because the block
protect bits prevent writing memory and the /WP
signal in hardware prevents altering the block protect
bits (if WPEN is high). Therefore in this condition,
hardware must be involved in allowing a write
operation. The following table summarizes the write
protection conditions.
Table 4. Write Protection
WEL
WPEN
/WP
Protected Blocks
Unprotected Blocks
Status Register
0
X
X
Protected
Protected
Protected
1
0
X
Protected
Unprotected
Unprotected
1
1
0
Protected
Unprotected
Protected
1
1
1
Protected
Unprotected
Unprotected
Memory Operation
The SPI interface, which is capable of a relatively
high clock frequency, highlights the fast write
capability of the FRAM technology. Unlike SPI-bus
EEPROMs, the FM25L512 can perform sequential
writes at bus speed. No page register is needed and
any number of sequential writes may be performed.
Write Operation
All writes to the memory array begin with a WREN
op-code. The next op-code is the WRITE instruction.
This op-code is followed by a two-byte address
value, which specifies the 16-bit address of the first
data byte of the write operation. Subsequent bytes are
data and they are written sequentially. Addresses are
incremented internally as long as the bus master
continues to issue clocks. If the last address of FFFFh
is reached, the counter will roll over to 0000h. Data is
written MSB first. A write operation is shown in
Figure 9.
Unlike EEPROMs, any number of bytes can be
written sequentially and each byte is written to
memory immediately after it is clocked in (after the
8
th
clock). The rising edge of /CS terminates a
WRITE op-code operation. Asserting /WP active in
the middle of a write operation will have no effect
until the next falling edge of /CS.
Read Operation
After the falling edge of /CS, the bus master can issue
a READ op-code. Following this instruction is a two-
byte address value, 16-bits specifying the address of
the first data byte of the read operation. After the op-
code and address are complete, the SI line is ignored.
The bus master issues 8 clocks, with one bit read out
for each. Addresses are incremented internally as
long as the bus master continues to issue clocks. If
the last address of FFFFh is reached, the counter will
roll over to 0000h. Data is read MSB first. The rising
edge of /CS terminates a READ op-code operation.
A read operation is shown in Figure 10.


Codice articolo simile - FM25L512

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
List of Unclassifed Man...
FM25L04 ETC-FM25L04 Datasheet
187Kb / 12P
   4Kb FRAM Serial 3V Memory
FM25L04-G ETC-FM25L04-G Datasheet
187Kb / 12P
   4Kb FRAM Serial 3V Memory
FM25L04-S ETC-FM25L04-S Datasheet
187Kb / 12P
   4Kb FRAM Serial 3V Memory
logo
Ramtron International C...
FM25L04B RAMTRON-FM25L04B Datasheet
208Kb / 14P
   4Kb Serial 3V F-RAM Memory
logo
Cypress Semiconductor
FM25L04B CYPRESS-FM25L04B Datasheet
469Kb / 14P
   4Kb Serial 3V F-RAM Memory
More results

Descrizione simile - FM25L512

Produttore elettroniciIl numero della parteScheda tecnicaSpiegazioni elettronici
logo
Ramtron International C...
FM24C512 RAMTRON-FM24C512 Datasheet
230Kb / 12P
   512Kb FRAM Serial Memory
FM25L16 RAMTRON-FM25L16_06 Datasheet
146Kb / 14P
   16Kb FRAM Serial 3V Memory
FM25CL64 RAMTRON-FM25CL64 Datasheet
131Kb / 13P
   64Kb FRAM Serial 3V Memory
FM25L256B RAMTRON-FM25L256B Datasheet
148Kb / 14P
   256Kb FRAM Serial 3V Memory
FM24CL64 RAMTRON-FM24CL64_07 Datasheet
115Kb / 13P
   64Kb Serial 3V FRAM Memory
logo
List of Unclassifed Man...
FM25CL04 ETC-FM25CL04 Datasheet
98Kb / 11P
   4Kb FRAM Serial 3V Memory
FM25L16 ETC-FM25L16 Datasheet
149Kb / 14P
   16Kb FRAM Serial 3V Memory
logo
Ramtron International C...
FM25CL64 RAMTRON-FM25CL64_07 Datasheet
137Kb / 13P
   64Kb FRAM Serial 3V Memory
logo
List of Unclassifed Man...
FM25L256 ETC-FM25L256 Datasheet
152Kb / 14P
   256Kb FRAM Serial 3V Memory
FM25L04 ETC-FM25L04 Datasheet
187Kb / 12P
   4Kb FRAM Serial 3V Memory
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


Scheda tecnica Scarica

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEETIT.COM
Lei ha avuto il aiuto da alldatasheet?  [ DONATE ] 

Di alldatasheet   |   Richest di pubblicita   |   contatti   |   Privacy Policy   |   scambio Link   |   Ricerca produttore
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com