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FM24C04A Scheda tecnica(PDF) 7 Page - Ramtron International Corporation |
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FM24C04A Scheda tecnica(HTML) 7 Page - Ramtron International Corporation |
7 / 12 page FM24C04A Rev. 3.0 Mar. 2005 7 of 12 S A Slave Address 1 Data Byte 1 P By Master By FM24C04A Start Address Stop Acknowledge No Acknowledge Data Figure 7. Current Address Read S A Slave Address 1 Data Byte 1 P By Master By FM24C04A Start Address Stop Acknowledge No Acknowledge Data Data Byte A Acknowledge Figure 8. Sequential Read S A Slave Address 1 Data Byte 1 P By Master By FM24C04A Start Address Stop No Acknowledge Data Data Byte A Acknowledge S A Slave Address 0 Word Address A Start Address Acknowledge Figure 9. Selective (Random) Read Endurance Internally, a FRAM operates with a read and restore mechanism. Therefore, endurance cycles are applied for each read or write cycle. The FRAM architecture is based on an array of rows and columns. Rows are defined by A8-A2. Each access causes an endurance cycle for a row. Endurance is virtually unlimited. At 3000 accesses per second to the same segment, it will take more than 10 years to reach the endurance limit. |
Codice articolo simile - FM24C04A_05 |
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Descrizione simile - FM24C04A_05 |
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