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FM3316 Scheda tecnica(PDF) 6 Page - Ramtron International Corporation |
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FM3316 Scheda tecnica(HTML) 6 Page - Ramtron International Corporation |
6 / 28 page FM33256/FM3316 SPI Companion w/ FRAM Rev. 1.0 Dec. 2006 Page 6 of 28 both sources indicated if both have occurred since the user cleared them. Power Fail Comparator An analog comparator compares the PFI input pin to an onboard 1.5V reference. When the PFI input voltage drops below this threshold, the comparator will drive the PFO pin to a low state. The comparator has 100 mV of hysteresis (rising voltage only) to reduce noise sensitivity. The most common application of this comparator is to create an early warning power fail interrupt (NMI). This can be accomplished by connecting the PFI pin to an upstream power supply via a resistor divider. An application circuit is shown below. The comparator is a general purpose device and its application is not limited to the NMI function. Figure 6. Comparator as a Power-Fail Warning If the power-fail comparator is not used, the PFI pin should be tied to either VDD or VSS. Note that the PFO output will drive to VDD or VSS as well. Event Counter The FM33xx offers the user a nonvolatile 16-bit event counter. The input pin CNT has a programmable edge detector. The CNT pin clocks the counter. The counter is located in registers 0E-0Fh. When the programmed edge polarity occurs, the counter will increment its count value. The register value is read by setting the RC bit (register 0Dh, bit 3) to 1. This takes a snapshot of the counter byte allowing a stable value even if a count occurs during the read. The register value can be written by first setting the WC bit (register 0Dh, bit 2) to 1. The user then may clear or preset the counter by writing to registers 0E-0Fh. Counts are blocked when the WC bit is set, so the user must clear the bit to allow counts. The counter polarity control bit is CP, register 0Dh bit 0. When CP is 0, the counter increments on a falling edge of CNT, and when CP is set to 1, the counter increments on a rising edge of CNT. The polarity bit CP is nonvolatile. Figure 7. Event Counter There is also a control bit that allows the user to define the counter as nonvolatile or battery-backed. The counter is nonvolatile when the NVC bit (register 0Dh, bit 7) is logic 1 and battery-backed when the NVC bit is logic 0. Setting the counter mode to battery-backed allows counter operation under VBAK (as well as VDD) power. The lowest operating voltage for battery-backed mode is 2.0V. When set to “nonvolatile” mode, the counter operates only when VDD is applied and is above the VTP voltage. The event counter may be programmed to detect a tamper event, such as the system’s case or access door being opened. A normally closed switch is tied to the CNT pin and the other contact to the case chassis, usually ground. The typical solution uses a pullup resistor on the CNT pin and will continuously draw battery current. The FM33xx chip allows the user to invoke a polled mode, which occasionally samples the pin in order to minimize battery drain. It internally tries to pull the CNT pin up and if open circuit will be pulled up to a VIH level, which will trip the edge detector and increment the event counter value. Setting the POLL bit (register 0Dh, bit 1) places the CNT pin into this mode. This mode allows the event counter to detect a rising edge tamper event but the user is restricted to operating in battery- backed mode (NVC=0) and using rising edge detection (CP=1). The CNT pin is polled once every 125ms. The additional average IBAK current is less than 5nA. The polling timer circuit operates from the RTC, so the oscillator must be enabled for this to function properly. Figure 8. Polled Mode on CNT pin Detects Tamper to System Case In the polled mode, the internal pullup circuit can source a limited amount of current. The maximum + - 1.5V ref Regulator VDD FM33xx To MCU NMI input PFO 16-bit Counter CNT CP CNT Vbak FM33xx 125ms < 100pF |
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