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74LVT126DB Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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74LVT126DB Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 15 page 9397 750 14553 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 04 — 11 February 2005 3 of 15 Philips Semiconductors 74LVT126 3.3 V quad buffer; 3-state 6. Pinning information 6.1 Pinning 6.2 Pin description (1) The die substrate is attached to the exposed die pad using conductive die attach material. It can not be used as a supply pin or input. Fig 3. Pin configuration SO14, SSOP14 and TSSOP14 Fig 4. Pin configuration DHVQFN14 126 VCC GND 001aac484 1 2 3 4 5 6 7 8 10 9 12 11 14 13 1A 1Y 1OE 2A 2Y 2OE 3A 3Y 3OE 4A 4Y 4OE 001aac485 126 Transparent top view 2Y 3A GND(1) 2A 3OE 2OE 4Y 1Y 4A 1A 4OE 6 9 5 10 4 11 3 12 2 13 terminal 1 index area Table 3: Pin description Symbol Pin Description 1OE 1 1 output enable input 1A 2 1 data input 1Y 3 1 data output 2OE 4 2 output enable input 2A 5 2 data input 2Y 6 2 data output GND 7 ground (0 V) 3Y 8 3 data output 3A 9 3 data input 3OE 10 3 output enable input 4Y 11 4 data output 4A 12 4 data input 4OE 13 4 output enable input VCC 14 supply voltage |
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