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SI8511-B-GM Scheda tecnica(PDF) 11 Page - Silicon Laboratories |
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SI8511-B-GM Scheda tecnica(HTML) 11 Page - Silicon Laboratories |
11 / 24 page Si85xx Preliminary Rev. 0.1 11 Figure 10. Full-Bridge Timing Example B 3.2.2. Selecting Reset Timing Signals Reset timing signals should be chosen to meet the following conditions: Satisfy reset time tR Not overlap integrator reset into the desired measurement period Not violate reset watchdog timeout period tWD 3.2.3. Configuring Integrator Reset Per Section “2. Functional Overview”, the integrator must be reset (zeroed) prior to the start of each measurement cycle to achieve specified measurement accuracy. This reset must be synchronized with the system switch timing signals to ensure current is measured during the appropriate time, so the Si85xx integrator reset circuitry uses system timing as its reference. Timing signals connect to reset inputs R1 through R4 where built-in logic functions allow the user to choose the conditions that cause an integrator reset event. Important note: reset inputs R1–R4 are rated to a maximum input voltage of VDD. External resistor dividers must be used when connecting driver output signals to R1–R4 that swing beyond VDD. R1 R3 R2 R4 MEASURE OUT1 OUT2 MEASURE RESET tR RESET tR |
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