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CS8420-CS Scheda tecnica(PDF) 9 Page - Cirrus Logic

Il numero della parte CS8420-CS
Spiegazioni elettronici  DIGITAL AUDIO SAMPLE RATE CONVERTER
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Produttore elettronici  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

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DS245F4
9
CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
7.
The active edges of ISCLK and OSCLK are programmable.
8.
When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.
9.
The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
Parameter
Symbol
Min
Typ
Max
Units
OSCLK Active Edge to SDOUT Output Valid
(Note 7)
tdpd
-
-
25
ns
SDIN Setup Time Before ISCLK Active Edge
(Note 7)
tds
20
-
-
ns
SDIN Hold Time After ISCLK Active Edge
(Note 7)
tdh
20
-
-
ns
Master Mode
O/RMCK to I/OSCLK active edge delay
(Note 7, 8)
tsmd
0
-
16
ns
O/RMCK to I/OLRCK delay
(Note 9)
tlmd
0
-
17
ns
I/OSCLK and I/OLRCK Duty Cycle
-
50
-
%
Slave Mode
I/OSCLK Period
(Note 10)
tsckw
36
-
-
ns
I/OSCLK Input Low Width
tsckl
14
-
-
ns
I/OSCLK Input High Width
tsckh
14
-
-
ns
I/OSCLK Active Edge to I/OLRCK Edge
(Note 7, 9, 11)
tlrckd
20
-
-
ns
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(Note 7, 9, 12)
tlrcks
20
-
-
ns
t
ILRCK
OLRCK
(input)
ISCLK
OSCLK
(input)
SDIN
SDOUT
t lrckd
lrcks
t sckh
tsckw
t sckl
tdpd
dh
t
ds
t
t
sm d
t
lm d
H ardware M ode
Softw are M ode
ISC LK
OSCLK
(output)
ILRCK
O LRCK
(output)
RM CK
(output)
RM CK
(output)
OM CK
(input)
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing


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