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CS5342 Scheda tecnica(PDF) 10 Page - Cirrus Logic |
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CS5342 Scheda tecnica(HTML) 10 Page - Cirrus Logic |
10 / 21 page 10 DS608F1 CS5342 SWITCHING CHARACTERISTICS - SERIAL AUDIO PORT (Logic "0" = GND = 0 V; Logic "1" = VL, CL = 20 pF) 10. For a description of speed modes, please refer to Table 1 on page 14 11. SCLK must be derived synchronously from MCLK and the ratio of SCLK/LRCK must be equal to 48. Parameter Symbol Min Typ Max Unit MCLK Specifications MCLK Period tclkw 26 - 30 ns 52 - 1302 ns MCLK Pulse Duty Cycle 40 - 60 % Master Mode SCLK falling to LRCK tmslr -20 - 20 ns SCLK falling to SDOUT valid tsdo -- 32 ns SCLK Duty Cycle Single-Speed Double-Speed Quad-Speed - - - 50 50 33 - - - % % % Slave Mode Single-Speed (Note 10) LRCK Duty Cycle 40 - 60 % SCLK Period tsclkw 313 - - ns SCLK Duty Cycle 45 - 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -20 - 20 ns Double-Speed (Note 10) LRCK Duty Cycle 40 - 60 % SCLK Period (Note 11) tsclkw 208 - - ns SCLK Duty Cycle 45 - 55 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -20 - 20 ns Quad-Speed (Note 10) LRCK Duty Cycle 40 - 60 % SCLK Period (Note 11) tsclkw 104 - - ns SCLK Duty Cycle 40 - 50 % SDOUT valid before SCLK rising tstp 10 - - ns SDOUT valid after SCLK rising thld 5- - ns SCLK falling to LRCK edge tslrd -8 - 8 ns |
Codice articolo simile - CS5342_06 |
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Descrizione simile - CS5342_06 |
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