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TEA1210 Scheda tecnica(PDF) 5 Page - NXP Semiconductors |
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TEA1210 Scheda tecnica(HTML) 5 Page - NXP Semiconductors |
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5 / 20 page  1999 Mar 08 5 Philips Semiconductors Preliminary specification High efficiency, high current DC/DC converter TEA1210TS PINNING For all possible applications, the following groups of pins must be connected together: • Pins 4, 5, 12 and 13 (pins LX) • Pins 1 and 16 (pins UPOUT) • Pins 8 and 9 (pins GND). SYMBOL PIN DESCRIPTION UPOUT 1, 16 output voltage in up mode; input voltage in down mode SYNC 2 synchronization clock input SHDWN 3 shut-down input LX 4, 5, 12, 13 inductor connection U/D 6 up-or-down mode selection input; active LOW for up mode ILIMH 7 current limiting resistor 1 connection GND 8, 9 ground ILIML 10 current limiting resistor 2 connection ILIMSEL 11 current limiting selection input PWM 14 PWM-only mode selection input FB 15 feedback input Fig.2 Pin configuration. handbook, halfpage TEA1210TS MGR726 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 UPOUT SYNC SHDWN LX LX U/D ILIMH GND GND ILIML ILIMSEL LX LX PWM FB UPOUT FUNCTIONAL DESCRIPTION Control mechanism The TEA1210TS DC/DC converter is able to operate in PFM (discontinuous conduction) or PWM (continuous conduction) operating mode. All switching actions are completely determined by a digital control circuit which uses the output voltage level as its control input. This novel digital approach enables the use of a new pulse width and frequency modulation scheme, which ensures optimum power efficiency over the complete operating range of the converter. When high output power is requested, the device will operate in PWM (continuous conduction) operating mode. This results in minimum AC currents in the circuit components and hence optimum efficiency, cost and EMC. In this operating mode, the output voltage is allowed to vary between two predefined voltage levels. As long as the output voltage stays within this so-called window, switching continues in a fixed pattern. When the output voltage reaches one of the window borders, the digital controller immediately reacts by adjusting the pulse width and inserting a current step in such a way that the output voltage stays within the window with higher or lower current capability. This approach enables very fast reaction to load variations. Figure 3 shows the converter’s response to a sudden load increase. The upper trace shows the output voltage. The ripple on top of the DC level is a result of the current in the output capacitor, which changes in sign twice per cycle, times the capacitor’s internal Equivalent Series Resistance (ESR). After each ramp-down of the inductor current, i.e. when the ESR effect increases the output voltage, the converter determines what to do in the next cycle. As soon as more load current is taken from the output the output voltage starts to decay. When the output voltage becomes lower than the low limit of the window, a corrective action is taken by a ramp-up of the inductor current during a much longer time. As a result, the DC current level is increased and normal PWM control can continue. The output voltage (including ESR effect) is again within the predefined window. Figure 4 depicts the spread of the output voltage window. The absolute value is most dependent on spread, while the actual window size is not affected. For one specific device, the output voltage will not vary more than 2% typically. In low output power situations, the TEA1210TS will switch over to PFM (discontinuous conduction) operating mode in case the PWM-only mode is not active. |
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