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TDA9855WP Scheda tecnica(PDF) 3 Page - NXP Semiconductors |
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TDA9855WP Scheda tecnica(HTML) 3 Page - NXP Semiconductors |
3 / 52 page 1997 Nov 04 3 Philips Semiconductors Product specification I2C-bus controlled BTSC stereo/SAP decoder and audio processor TDA9855 QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VCC supply voltage 8.0 8.5 9.0 V ICC supply current 50 75 95 mA VCOMP(rms) input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − 250 − mV VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz − 500 − mV GLA input level adjustment control maximum gain − 4 − dB maximum attenuation −−3.5 − dB α cs stereo channel separation fL = 300 Hz; fR = 3 kHz 25 35 − dB THDL,R total harmonic distortion L + R fi = 1 kHz − 0.2 − % VI, O(rms) signal handling (RMS value) THD < 0.5% 2 −− V AVL control range −15 − +6 dB Gc volume control range −71 − +16 dB LB maximum loudness boost fi =40Hz − 17 − dB Gbass bass control range fi =40Hz −12 − +16.5 dB Gtreble treble control range fi = 15 kHz −12 − +12 dB Gs subwoofer control range fi =40Hz −14 − +14 dB S/N signal-to-noise ratio line out (mono); Vo = 0.5 V (RMS) CCIR noise weighting filter (peak value) − 60 − dB DIN noise weighting filter (RMS value) − 73 − dBA audio section; Vo = 2 V (RMS); gain = 0 dB CCIR noise weighting filter (peak value) − 94 − dB DIN noise weighting filter (RMS value) − 107 − dBA |
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