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AM79574-2JC Scheda tecnica(PDF) 11 Page - Advanced Micro Devices |
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AM79574-2JC Scheda tecnica(HTML) 11 Page - Advanced Micro Devices |
11 / 17 page SLIC Products 11 11. Assumes the following ZT network: 12. Tested with 0 Ω source impedance. 2 MΩ is specified for system design purposes only. 13. Group delay can be considerably reduced by using a ZT network such as that shown in Note 11 above. The network reduces the group delay to less than 2 µs. The effect of group delay on linecard performance may be compensated for by using QSLAC™ or DSLAC™ devices. Note: * A logic Low on E0 disables the DET output into the Open Collector state. Table 1. SLIC Decoding DET Output State C3 C2 C1 Two-Wire Status E0 = 1* E1 = 0 E0 = 1* E1 = 1 0 0 0 0 Open Circuit Ring trip Ring trip 1 0 0 1 Ringing Ring trip Ring trip 2 0 1 0 Active Loop detector Ground key 3 0 1 1 On-hook TX (OHT) Loop detector Ground key 4 1 0 0 Tip Open Loop detector — 5 1 0 1 Reserved Loop detector — 6 1 1 0 Active Polarity Reversal Loop detector Ground key 7 1 1 1 OHT Polarity Reversal Loop detector Ground key Table 2. User-Programmable Components ZT is connected between the VTX and RSN pins. The fuse resistors are RF, and Z2WIN is the desired 2-wire AC input impedance. When computing ZT, the internal current amplifier pole and any external stray capacitance between VTX and RSN must be taken into account. ZRX is connected from VRX to the RSN pin, ZT is defined above, and G42L is the desired receive gain. RDC1, RDC2, and CDC form the network connected to the RDC pin. RDC1 and RDC2 are approximately equal. RD and CD form the network connected from RD to –5 V and IT is the threshold current between on hook and off hook. VTX RSN 300 k Ω 300 k Ω 30 pF Z T 1000 Z 2WIN 2R F – () = Z RX Z L G 42L ----------- 1000 Z T • Z T 1000 Z L 2R F + () + ---------------------------------------------------- • = R DC 1 R DC2 50 R FEED 2R F – () = + C DC 1.5 ms R DC1 R DC 2 + R DC 1 R DC2 • -------------------------------- • = R D 365 I T --------- C D 0.5 ms R D ------------------ = , = |
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