TDA8753A datasheet(6/20 Pages) PHILIPS

Il numero della parte	TDA8753A

Spiegazioni elettronici	YUV 8-bit analog-to-digital interface

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Produttore elettronici	PHILIPS [NXP Semiconductors]

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6 / 20 page

1996 Jan 12

6

Philips Semiconductors

Product speciﬁcation

YUV 8-bit analog-to-digital interface

TDA8753A

The TDA8753A registers have address F0, F1 and F2

hexadecimal notation. Whenever the received address

(decoded on the first 8 bits received) is one of these, the

event is recorded in such a way that the next data received

by the TDA8753A will be captured in the line

buffer BF0, BF1 and BF2 respectively.

When 8 bits have been received, the data reception state

is entered. The address reception state can also be exited

at any time when V50 goes HIGH. The F0, F1 and F2

registers may not be loaded properly if there is some

activity in progress on the incoming line.

DATA RECEPTION STATE

The next 8 bits are considered as data bits according to

the format of Fig.4.

When 8 data bits have been received, the data is recorded

in the BF0, BF1 or BF2 line buffers if the previous address

recorded was F0 hex, F1 hex or F2 hex respectively.

The bit count is then reset to zero and the address

reception state is entered. This state may be ended any

time when V50 goes HIGH but in that condition F0, F1 and

F2 registers may not be loaded properly.

Table 1

Data allocation

ADDRESS

PARAMETER

FUNCTION

NUMBER

OF BITS

BIT

POSITION

F0H

CF

compression factor value will be (1 + cf/255)

which results in a range from 1 to 2

8

7:0

F1H

UV_CORING

coring deﬁnition in U and V channels; see Table 5

2

1:0

UV_FILTER_TYPE

notch ﬁlter selection in U and V channels

(0 = 4 MHz; 1 = 2 MHz)

12

PRE_ON

luminance preﬁlter active

1

3

NOTCH_ON

notch preﬁlter active

1

4

DTO_ON

DTO control

1

5

SEL_DTO_RES

select DTO reset (0 = WE; 1 = Href)1

6

WEO_DEL_SEL

select delay in WEO

F2H

Y_VAR_DELAY

luminance delay compression (see Table 5)

not used; load 0

5

7:2

Fig.4 Data reception.

handbook, halfpage

1

0

XX

X

MBE427

last address

bit received

first data bit of value

(e.g. for address F2 register)

first bit of next

address stream

Data value is F2

0:2

= 110(DEL 0:2

)

incoming stream

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