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STK17T88 Scheda tecnica(PDF) 1 Page - Simtek Corporation |
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STK17T88 Scheda tecnica(HTML) 1 Page - Simtek Corporation |
1 / 28 page STK17T88 1 This product conforms to specifications per the terms of Simtek standard warranty. The product has completed Simtek internal qualification testing and has reached production status. March 2007 Document Control #ML0024 Rev 1.7 FEATURES • nvSRAM Combined With Integrated Real-Time Clock Functions (RTC, Watchdog Timer, Clock Alarm, Power Monitor) • Capacitor or Battery Backup for RTC • 25, 45 ns Read Access & R/W Cycle Time • Unlimited Read/Write Endurance • Automatic Non-volatile STORE on Power Loss • Non-Volatile STORE Under Hardware or Soft- ware Control • Automatic RECALL to SRAM on Power Up • Unlimited RECALL Cycles • 200K STORE Cycles • 20-Year Non-volatile Data Retention • Single 3 V + 20%, -10% Power Supply • Commercial and Industrial Temperatures • Small Footprint SSOP Package (RoHS-Compli- ant) DESCRIPTION The Simtek STK17T88 combines a 256Kb non-vola- tile static RAM (nvSRAM) with a full-featured real- time clock in a reliable, monolithic integrated circuit. The 256Kbit nvSRAM is a fast static RAM with a non-volatile Quantum Trap storage element included with each memory cell. The SRAM provides the fast access & cycle times, ease of use and unlimited read & write endurance of a normal SRAM. Data transfers automatically to the non-volatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control. The real time clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The Alarm function is pro- grammable for one-time alarms or periodic minutes, hours, or days alarms. There is also a programma- ble watchdog timer for processor control. 32K x 8 AutoStore nvSRAM COLUMN DEC G E W COLUMN I/O POWER CONTROL HSB STORE/ RECALL CONTROL SOFTWARE DETECT A13 – A0 STORE RECALL DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VCC VCAP RTC MUX A14 – A0 X1 X2 INT VRTCbat VRTCcap A5 A6 A7 A8 A9 A11 A12 A13 A14 A0 A1 A2 A3 A4 A10 Quantum Trap 512 X 512 STATIC RAM ARRAY 512 X 512 BLOCK DIAGRAM |
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