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TC7109IJL Scheda tecnica(PDF) 6 Page - Microchip Technology |
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TC7109IJL Scheda tecnica(HTML) 6 Page - Microchip Technology |
6 / 30 page TC7109/A DS21456C-page 6 © 2006 Microchip Technology Inc. 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number (40-Pin PDIP) Symbol Description 1 GND Digital ground, 0V, ground return for all digital logic. 2 STATUS Output HIGH during integrate and de-integrate until data is latched. Output LOW when analog section is in auto-zero or zero integrator configuration. 3 POL Polarity – High for positive input. 4 OR Over Range – High if over ranged (Three-State Data bit). 5B12 Bit 12 (Most Significant bit) (Three-State Data bit). 6B11 Bit 11 (Three-State Data bit). 7B10 Bit 10 (Three-State Data bit). 8B9 Bit 9 (Three-State Data bit). 9B8 Bit 8 (Three-State Data bit). 10 B7 Bit 7 (Three-State Data bit). 11 B6 Bit 6 (Three-State Data bit). 12 B5 Bit 5 (Three-State Data bit). 13 B4 Bit 4 (Three-State Data bit). 14 B3 Bit 3 (Three-State Data bit). 15 B2 Bit 2 (Three-State Data bit). 16 B1 Bit 1 (Least Significant bit) (Three-State Data bit). 17 TEST Input High – Normal operation. Input LOW – Forces all bit outputs HIGH. Note: This input is used for test purposes only. 18 LBEN Low Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates low order byte outputs, B1–B8. With MODE (Pin 21) HIGH, this pin serves as low byte flag output used in Handshake mode. (See Figure 3-7, Figure , and Figure 3-9.) 19 HBEN High Byte Enable – with MODE (Pin 21) LOW, and CE/LOAD (Pin 20) LOW, taking this pin LOW activates high order byte outputs, B9–B12, POL, OR. With MODE (Pin 21) HIGH, this pin serves as high byte flag output used in Handshake mode. See Figures 3-7, 3-8, and 3-9. 20 CE/LOAD Chip Enable/Load – with MODE (Pin 21) LOW, CE/LOAD serves as a master output enable. When HIGH, B1–B12, POL, OR outputs are disabled. When MODE (Pin 21) is HIGH, a load strobe is used in handshake mode. (See Figure 3-7, Figure , and Figure 3-9.) 21 MODE Input LOW – Direct Output mode where CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) act as inputs directly controlling byte outputs. Input Pulsed HIGH - Causes immediate entry into Handshake mode and output of data as in Figure 3-9. Input HIGH – enables CE/LOAD (Pin 20), HBEN (Pin 19), and LBEN (Pin 18) as outputs, Handshake mode will be entered and data output as in Figure 3-7 and Figure 3-9 at conversions completion. 22 OSC IN Oscillator Input. 23 OSC OUT Oscillator Output. 24 OSC SEL Oscillator Select – Input HIGH configures OSC IN, OSC OUT, BUFF OSC OUT as RC oscillator – clock will be same phase and duty cycle as BUFF OSC OUT. Input LOW configures OSC IN, OSC OUT for crystal oscillator - clock frequency will be 1/58 of frequency at BUFF OSC OUT. 25 BUFF OSC OUT Buffered Oscillator Output. 26 RUN/HOLD Input HIGH – Conversions continuously performed every 8192 clock pulses. Input LOW – Conversion in progress completed; converter will stop in auto-zero seven counts before integrate. 27 SEND Input - Used in Handshake mode to indicate ability of an external device to accept data. Connect to V+ if not used. 28 V- Analog Negative Supply – Nominally -5V with respect to GND (Pin 1). 29 REF OUT Reference Voltage Output – Nominally 2.8V down from V+ (Pin 40). |
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