TDA8357 datasheet(7/16 Pages) PHILIPS

Il numero della parte	TDA8357

Spiegazioni elettronici	Full bridge vertical deflection output circuit in LVDMOS

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Produttore elettronici	PHILIPS [NXP Semiconductors]

Homepage	http://www.nxp.com

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7 / 16 page

1999 Nov 10

7

Philips Semiconductors

Preliminary speciﬁcation

Full bridge vertical deﬂection output circuit

in LVDMOS

TDA8357J

Notes

1. To limit VOUTA to 68 V, VFB must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA

and VFB at the first part of the flyback.

2. Allowable input range: VI(bias) +Vi(dif) < 1600 mV and VI(bias) − Vi(dif) > 100 mV for each input.

3. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTA, and

between pins OUTB and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(1) is a positive value.

4. This value specifies the sum of the voltage losses of the internal current paths between pins VP and OUTB, and

between pins OUTA and GND. Specified for Tj = 125 °C. The temperature coefficient for Vloss(2) is a positive value.

5. The linearity error is measured for a linear input signal without S-correction and is based on the ‘on screen’

measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time

blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across RM, starting at

k = 2 and ending at k = 21, where Vk and Vk+1 are the measured voltages of two successive blocks. Vmin,Vmax and

Vavg are the minimum, maximum and average voltages respectively. The linearity errors are defined as:

a)

(adjacent blocks)

b)

(non adjacent blocks)

6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage

dependent S-distortion in the input stage.

7.

8. Pin FEEDB not connected.

9.

10. VP(ripple) = 500 mV (RMS value); 50 Hz < fP(ripple) < 1 kHz; measured across RM.

11. This value specifies the internal voltage loss of the current path between pins VFB and OUTA.

Flyback switch

Io(peak)

maximum (peak) output current

t

≤ 1.5 ms

−−±1.2

A

Vloss(FB)

voltage loss at ﬂyback

note 11

Io = 0.7 A

−

7.5

8.5

V

Io = 1.0 A

−

89V

Guard circuit

VO(grd)

guard output voltage

IO(grd) = 100 µA

567V

VO(grd)(max) allowable guard voltage

maximum leakage current

IL(max) =10 µA

−−

18

V

IO(grd)

output current

VO(grd) = 0 V; not active

−−

10

µA

VO(grd) = 4.5 V; active

1

−

2.5

mA

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

LE

V

k

V

k1

+

–

V

avg

--------------------------

=

LE

V

max

V

min

–

V

avg

-------------------------------

=

G

vol

()

V

OUTA

V

OUTB

–

V

FEEDB

V

OUTB

–

--------------------------------------------

=

G

v

V

FEEDB

V

OUTB

–

V

INA

V

INB

–

--------------------------------------------

=

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