1998 Sep 03

5

Philips Semiconductors

Preliminary specification

Full bridge current driven vertical deflection

output circuit in LVDMOS

TDA8354Q

Guard circuit

The guard circuit generates an active HIGH level during

the flyback period. The guard circuit is also activated for

one or more of the following conditions:

• During short-circuit of the output pins (pins 5 and 9) to

• During open coil

• During open loop

• During short-circuit of the input pins (pins 11 and 12) to

An active HIGH level of the guard signal is also generated

for the next conditions:

• No drive signal

• Short-circuit of the coil.

However, for these events the signal is generated via an

internal timer circuit. The guard signal set via this timer has

a delay of

≈120 ms. The delay time is given by the lowest

applicable field frequency.

The guard signal can be used for blanking the picture tube

screen and signalling a fault condition.

Damping resistor compensation

For HF-loop stability a damping resistor is connected

across the deflection coil. There is a big difference in

The resistor current is summed to the current in the

in a too low current in the deflection coil at the start of the

scan.

To reach a short settling time the difference in the current

during scan and flyback in the damping resistor can be

compensated for by external means. To do so a resistor

output of stage A (pin 9) and the damping resistor

compensation current input (pin 13).

following formula:

R

comp

V

flb

V

loss

–

V

P

–

() R

p

×

R

con

×

V

flb

V

loss

–

I

L

R

L

×

–

() R

M

×

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