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TDA4854 Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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TDA4854 Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
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8 / 60 page  1999 Jul 13 8 Philips Semiconductors Product specification I2C-bus autosync deflection controllers for PC/TV monitors TDA4853; TDA4854 Video clamping/vertical blanking generator The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitable for video ICs such as the TDA488x family, but also for direct applications in video output stages. The upper level is the video clamping pulse, which is triggered by the horizontal sync pulse. Either the leading or trailing edge can be selected by setting control bit CLAMP via the I2C-bus. The width of the video clamping pulse is determined by an internal single-shot multivibrator. The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Two different vertical blanking times are accessible, by control bit VBLK, via the I2C-bus. Blanking will be activated continuously if one of the following conditions is true: Soft start of horizontal and B+ drive [voltage at HPLL2 (pin 30) pulled down externally or by the I2C-bus] PLL1 is unlocked while frequency-locked loop is in search mode or if horizontal sync pulses are absent No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Supply voltage at VCC (pin 10) is low (see Fig.25). Horizontal unlock blanking can be switched off, by control bit BLKDIS, via the I2C-bus while vertical blanking and protection blanking is maintained. Frequency-locked loop The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the recommended maximum ratio is This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included. Without a horizontal sync signal the oscillator will be free-running at fmin. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency will switch the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures smooth tuning and avoids fast changes of horizontal frequency during catching. In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor connected between pins HBUF and HREF defines the frequency range. Out-of-lock indication (pin HUNLOCK) Pin HUNLOCK is floating during search mode if no sync pulses are applied, or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage. For an additional fast vertical blanking at grid 1 of the picture tube a 1 V signal referenced to ground is available at this output. The continuous protection blanking (see Section “Video clamping/vertical blanking generator”) is also available at this pin. Horizontal unlock blanking can be switched off, by control bit BLKDIS via the I2C-bus while vertical blanking is maintained. TV mode In applications with TV signals the standard frequency-to-voltage converter operation will be disturbed by equalizing sync pulses and phase jumps occurring in VCR signals. To avoid this, a TV mode has been implemented. It can be accessed by choosing the horizontal TV sync frequencies of 15.625 or 15.75 kHz as the minimum frequency for the horizontal oscillator. Applying TV signals will cause the frequency-to-voltage converter to scan down to this frequency in normal operation. If the control bit TVMOD is sent by the I2C-bus, the HBUF output is clamped to 2.5 V and an internally defined PLL1 control range of ±10% is established. To return to standard operation of the frequency-to-voltage converter the bit TVMOD has to be reset. For an optimal operation with VCR signals the RC combination at pin HPLL1 has to be switched externally. f max f min ---------- 6.5 1 -------- = |
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