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TDA4853 Scheda tecnica(PDF) 7 Page - NXP Semiconductors |
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TDA4853 Scheda tecnica(HTML) 7 Page - NXP Semiconductors |
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7 / 60 page  1999 Jul 13 7 Philips Semiconductors Product specification I2C-bus autosync deflection controllers for PC/TV monitors TDA4853; TDA4854 Fig.3 Pin configuration for TDA4853. handbook, halfpage TDA4853 MGM066 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 HFLB XRAY BOP BSENS BIN BDRV PGND HDRV XSEL VCC EWDRV VOUT2 VOUT1 VSYNC i.c. HSMOD HPLL2 HCAP HBUF HPLL1 HREF SGND VCAP VREF VAGC VSMOD ASCOR SDA HSYNC CLBL SCL HUNLOCK Fig.4 Pin configuration for TDA4854. handbook, halfpage TDA4854 MGM067 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 HFLB XRAY BOP BSENS BIN BDRV PGND HDRV XSEL VCC EWDRV VOUT2 VOUT1 VSYNC FOCUS HSMOD HPLL2 HCAP HBUF HPLL1 HREF SGND VCAP VREF VAGC VSMOD ASCOR SDA HSYNC CLBL SCL HUNLOCK FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to top sync. For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V. The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and normalize the sync polarity. Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop. The presence of equalization pulses is allowed for correct function of the PLL1 phase detector only in TV mode. Vertical sync integrator Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator. Vertical sync slicer and polarity correction Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity. The output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator. |
Codice articolo simile - TDA4853 |
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Descrizione simile - TDA4853 |
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