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TDA4852 Scheda tecnica(PDF) 8 Page - NXP Semiconductors |
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TDA4852 Scheda tecnica(HTML) 8 Page - NXP Semiconductors |
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8 / 16 page  December 1992 8 Philips Semiconductors Preliminary specification Horizontal and vertical deflection controller for autosync monitors TDA4852 Vertical sync input (DC-coupled, TTL-compatible) V-sync on pin 10 Vi sync sync input signal (peak-to-peak value, pin 10) 1.7 −− V slicing level 1.2 1.4 1.6 V I10 input current 0 < V10 < 5.5 V −− ±10 µA tp V maximum vertical sync pulse width for automatic vertical polarity switch −− 300 µs Horizontal clamping / blanking generator output Fig.6 V8 output voltage LOW −− 0.9 V blanking output voltage internal V blanking 1.6 1.9 2.2 V clamping output voltage H-sync on pin 9 5.15 5.4 5.65 V I8 internal sink current for all output levels H and V scanning 2.3 2.9 3.5 mA external load current −− −3.0 mA t8 clamping pulse start with end of H-sync tclp clamping pulse width V8 = 3 V 0.6 0.8 1.0 µs S steepness of rise and fall times − 60 75 ns/V Vertical oscillator Vref = 6.25 V f0 vertical free-running frequency R15 = 22 kΩ; C16 = 0.1 µF − 42 − Hz fv nominal vertical sync range no f0 adjustment 50 − 110 Hz V15 voltage on pin 15 R15 = 22 kΩ 2.8 3.0 3.2 V td delay between sync pulse and start of vertical scan measured on pin 8 240 300 360 µs I12 control current for amplitude control −±200 −µA C12 capacitor for amplitude control −− 0.18 µF Vertical differential output Fig.7 Io differential output current between pins 5 and 6 (peak-to-peak value) mode 3; I13 >−135 µA; R15 = 22 kΩ 0.9 1.0 1.1 mA maximum offset-current error Io = 1 mA −− ±2.5 % maximum linearity error −− ±1.5 % Vertical amplitude adjustment (in percentage of output signal) V13 input voltage − 5.0 − V I13 adjustment current Io max (100%) −110 −120 −135 µA Io min (typically 58%) − 0 −µA Horizontal comparator PLL1 V17 upper control voltage limitation − 5.9 − V lower control voltage limitation − 5.1 − V I17 control current Fig.6 −±0.083I18 − mA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT |
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