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KMPC885ZP66 Scheda tecnica(PDF) 3 Page - Freescale Semiconductor, Inc |
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KMPC885ZP66 Scheda tecnica(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 92 page MPC885/MPC880 Hardware Specifications, Rev. 3 Freescale Semiconductor 3 Features — UTOPIA L2-compliant interface with added FIFO buffering to reduce the total cell transmission time and multi-PHY support. (The earlier UTOPIA L1 specification is also supported.) — Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode — Supports full-duplex UTOPIA master (ATM side) and slave (PHY side) operations using a split bus — AAL2/VBR functionality is ROM-resident. • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits) • 32 address lines • Memory controller (eight banks) — Contains complete dynamic RAM (DRAM) controller — Each bank can be a chip select or RAS to support a DRAM bank. — Up to 30 wait states programmable per memory bank — Glueless interface to DRAM, SIMMS, SRAM, EPROMs, Flash EPROMs, and other memory devices — DRAM controller programmable to support most size and speed memory interfaces — Four CAS lines, four WE lines, and one OE line — Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory) — Variable block sizes (32 Kbyte–256 Mbyte) — Selectable write protection — On-chip bus arbitration logic • General-purpose timers — Four 16-bit timers or two 32-bit timers — Gate mode can enable/disable counting. — Interrupt can be masked on reference match and event capture • Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that interface through MII and/or RMII interfaces • System integration unit (SIU) — Bus monitor — Software watchdog — Periodic interrupt timer (PIT) — Clock synthesizer — Decrementer and time base — Reset controller — IEEE 1149.1 test access port (JTAG) • Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP, 802.11i, and iSCSI processing. Available on the MPC885, the security engine contains a crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are: — Data encryption standard execution unit (DEU) – DES, 3DES – Two key (K1, K2, K1) or three key (K1, K2, K3) – ECB and CBC modes for both DES and 3DES |
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