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CD74HCT670M96 Scheda tecnica(PDF) 2 Page - Texas Instruments |
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CD74HCT670M96 Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 17 page 2 Functional Diagram 9 6 7 10 Q0 Q1 Q2 Q3 4 11 15 1 3 D0 D2 WE RE 514 13 RA1 RA0 WA0 WA1 12 2 D1 D3 WRITE MODE SELECT TABLE OPERATING MODE INPUTS INTERNAL LATCHES (NOTE 1) WE DN Write Data L L L LH H Data Latched H X No Change NOTE: 1. The Write Address (WA0 and WA1) to the “internal latches” must be stable while WE is LOW for conventional operation. READ MODE SELECT TABLE OPERATING MODE INPUTS OUTPUT QN RE INTERNAL LATCHES (NOTE 2) Read L L L LH H Disabled H X (Z) NOTE: 2. The selection of the “internal latches” by Read Address (RA0 and RA1) are not constrained by WE or RE operation. H = High Voltage Level L = Low Voltage Level X= Don’t Care Z = High Impedance “Off” State CD54HC670, CD74HC670, CD74HCT670 CD54HC670, CD74HC670, CD74HCT670 |
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