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TSC2007IPWG4 Scheda tecnica(PDF) 8 Page - Texas Instruments

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Il numero della parte TSC2007IPWG4
Spiegazioni elettronici  1.2V to 3.6V, 12-Bit, Nanopower, 4-Wire Micro TOUCH SCREEN CONTROLLER with I2C??Interface
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Produttore elettronici  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

TSC2007IPWG4 Scheda tecnica(HTML) 8 Page - Texas Instruments

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TSC2007
SBAS405 – MARCH 2007
TIMING REQUIREMENTS: I2C High-Speed Mode (SCL = 3.4MHz)
All specifications typical at –40
°C to +85°C, V
DD = 1.6V, unless otherwise noted.
2-WIRE HIGH-SPEED MODE PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SCL clock frequency
fSCL
0
3.4
MHz
Hold time (repeated) START condition
tHD, STA
160
ns
Low period of SCL clock
tLOW
160
ns
High period of the SCL clock
tHIGH
60
ns
Setup time for a repeated START condition
tSU, STA
160
ns
Data hold time
tHD, DAT
0
70
ns
Data setup time
tSU, DAT
10
ns
Rise time for SCL clock signal (receiving)
tR
Cb = total bus capacitance
10
40
ns
Rise time for SDA clock signal (receiving)
tR
Cb = total bus capacitance
10
80
Fall time for SCL clock signal (receiving)
tF
Cb = total bus capacitance
10
40
ns
Fall time for SDA clock signal (receiving)
tF
Cb = total bus capacitance
10
80
Fall time for both SDA and SCL clock signals (transmitting)
tOF
Cb = total bus capacitance
10
80
ns
Setup time for STOP condition
tSU, STO
160
ns
Capacitive load for each bus line
Cb
Cb = total capacitance of one bus line in pF
100
pF
8 bits
40 SCL + 127 CCLK, VDD = 1.8V
46.5
µs
Cycle time
12 bits
49 SCL + 148 CCLK, VDD = 1.8V
95.3
µs
8 bits
VDD = 1.8V
21.52
kSPS
Effective throughput
12 bits
VDD = 1.8V
10.49
kSPS
8 bits
VDD = 1.8V
150.65
kHz
Equivalent rate = effective throughput
× 7
12 bits
VDD = 1.8V
73.46
kHz
8
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