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AD9937KCPRL Scheda tecnica(PDF) 9 Page - Analog Devices

Il numero della parte AD9937KCPRL
Spiegazioni elettronici  CCD Signal Processor with Precision Timing??Generator
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Produttore elettronici  AD [Analog Devices]
Homepage  http://www.analog.com
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AD9937KCPRL Scheda tecnica(HTML) 9 Page - Analog Devices

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AD9937
–9–
Table I. Control Register Map
Bit
Bit
Register
Addr
Breakdown Width
Default
Name
Function
0
(23:0)
24
0
SW_RESET
Software Reset = 000000 (Reset All Registers to Default).
10
10
OUTCONT_REG
Internal OUTCONT Signal Control (0 = Digital Outputs held
at fixed dc level, 1 = Normal Operation).
(23:1)
23
Unused
2(1:0)
2
0
AFE_STBY
AFE Standby (0 = Full Standby, 1 = Normal Operation,
2/3 = Reference Standby).
21
0DIG_STBY
Digital Standby (0 = Full Standby, 1 = Normal Operation).
(23:3)
21
Unused
3(7:0)
8
0x80
REFBLACK
Black Clamp Level.
81
1
BC_EN
1 = Black Clamp Enable.
91
0
TESTMODE
This register should always be set to 0.
10
1
0
TESTMODE
This register should always be set to 0.
11
1
0
PBLK_LEVEL
0 = Blank to 0, 1 = Blank to Clamp Level (REFBLACK).
12
1
0
TRISTATEOUT
0 = Data Outputs are Driven, 1 = Data Outputs are Three-Stated.
13
10
RETIMEOUT_BAR 0 = Retime Data Outputs, 1 = Do Not Retime Data Outputs.
14
1
0
GRAY_ENCODE
1 = Gray Encode ADC Outputs.
(16:15)
2
0
TESTMODE
This register should always be set to 0.
17
1
0
TESTMODE
This register should always be set to 0.
18
1
1
TESTMODE
This register should always be set to 1.
(23:19)
5
Unused
40
10
VCKM_DIVIDE
VCKM Input Clock Divider (0 = VCKM, 1 = VCKM/2).
11
0
H1BLKRETIME
Retimes the H1 HBLK to Internal Clock.
21
0
LM_INVERT
LM Inversion Control (1 = Invert Programmed LM).
31
0
TGOFD_INVERT
TG and OFD Inversion Control (1 = Invert Programmed TG
and ODF).
41
0
VDHD_INVERT
VD and HD Inversion Control (1 = Invert Programmed VD
and HD; Note that Internal VD/HD Are HI Active).
51
0
MASTER
Operating Mode (0 = Slave Mode, 1 = Master Mode).
(23:6)
18
Unused
5(5:0)
6
0x00
SHDLOC
SHD Sample Location.
(11:6)
6
0x24
SHPLOC
SHP Sample Location.
(17:12)
6
0x00
DOUTPHASE
Data Output [9:0] and VCLK Phase Adjustment.
(19:18)
2
0x00
DOUT_DELAY
Data Output Clock Selection (0 = No Delay, 1 = ~4 ns, 2 = ~8 ns,
3 = ~12 ns).
20
1
0
VCLKMASK
VCLK Masking Control (1 = Mask).
21
1
1
VCLK_INVERT
1 = Invert VCLK.
22
1
0
DTEST
1 = Internal Digital Signal Test Mode.
23
1
Unused
6(5:0)
6
0x00
H1POSLOC
H1 Positive Edge Location.
(11:6)
6
0x20
H1NEGLOC
H1 Negative Edge Location.
(17:12)
6
0x00
RSPOSLOC
RS Positive Edge Location.
(23:18)
6
0x10
RSNEGLOC
RS Negative Edge Location.
7(2:0)
3
4
H1DRV
H1A/B/C/D Drive Strength (0 = OFF, 1 = 1.75 mA, 2 = 3.5 mA,
3 = 5.25 mA, 4 = 7 mA, 5 = 8.75 mA, 6 = 10.5 mA, 7 = 12.25 mA).
(5:3)
3
4
H2DRV
H2A/B Drive Strength (see H1DRV).
(8:6)
3
4
RSDRV
RS Drive Strength (see H1DRV).
(23:9)
15
Unused
(23:1)
23
Unused


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