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CDCE421YS Scheda tecnica(PDF) 2 Page - Texas Instruments |
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CDCE421YS Scheda tecnica(HTML) 2 Page - Texas Instruments |
2 / 30 page www.ti.com DESCRIPTION f xtal + OutputDivider FeedbackDivider fout (1) Crystal Oscillator Feedback Divider 12,16,20and32 Output Divider 1,2,4,8,16and32 PFD/ ChargePump Prescaler 2,3,4and5 LoopFilter VCO1 1890 VCO2 2200 XIN1 XIN2 CE SDATA B0217-01 1-Pin Interface and Control EEPROM LVPCL LVDS CDCE421 SCAS842 – APRIL 2007 The CDCE421 is a high-performance, low-phase-noise clock generator. It has two fully integrated, low-noise, LC-based voltage controlled oscillators (VCOs) that operate in the 1.750-GHz–2.350-GHz frequency range. It has an integrated crystal oscillator that operates in conjunction with an external AT-cut crystal to produce a stable frequency reference for the PLL-based frequency synthesizer. The output frequency (fout) is proportional to the frequency of the input crystal (fxtal). The prescaler divider, feedback divider, output divider, and VCO selection are what set (fout) with respect to (fxtal). For a desired frequency (fout), look in Table 1 and find the corresponding settings in the same row. Use Equation 1 to calculate the exact crystal oscillator frequency needed for the desired output. Output divider(1) = 1, 2, 4, 8, 16, or 32 Feedback divider(2) = 12, 16, 20, or 32 (1)Output divider and feedback divider should be from the same row in Table 1. (2)Feedback divider is set automatically with respect to the prescaler setting in Table 1. A high-level block diagram of the CDCE421 is shown in Figure 1. The CDCE421 supports one differential LVDS clock output or one differential LVPECL output. All device settings are programmable through a Texas Instruments proprietary simple serial interface. The device operates in a 3.3-V supply environment and is characterized for operation from –40 °C to 85°C. The CDCE421 is available in die form or in a QFN-24 package. Figure 1. High-Level Block Diagram of the CDCE421 In the CDCE421, the feedback divider is set automatically with respect to the prescaler setting. The product of the prescaler and the feedback divider will be either 60 or 64, as shown in Table 1, to keep the control loop stable. 2 Submit Documentation Feedback |
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