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CDCL1810RGZR Scheda tecnica(PDF) 7 Page - Texas Instruments |
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CDCL1810RGZR Scheda tecnica(HTML) 7 Page - Texas Instruments |
7 / 25 page www.ti.com CDCL1810 SLLS781A – FEBRUARY 2007 – REVISED MARCH 2007 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS TERMINAL NAME PIN NO. TYPE DESCRIPTION 8, 11, 14, 17, 20, 23, 26, VDD Power 1.8V digital power supply. 29, 32, 35, 38, 41 AVDD 2, 5, 44, 47 Power 1.8V analog power supply. Exposed VSS thermal pad Power Ground reference. and pin 12 1, 13, 45, 46, NC I Not connected; leave open. 48 Differential LVDS input. Single-ended 1.8-V input can be dc-coupled to pin 3 with pin 4 CLKP, CLKN 3, 4 I either tied to pin 3 (recommended) or left open. YP0, YN0 6, 7 YP1, YN1 9, 10 YP2, YN2 15, 16 YP3, YN3 18, 19 YP4, YN4 21, 22 O 10 differential CML outputs. YP5, YN5 27, 28 YP6, YN6 30, 31 YP7, YN7 33, 34 YP8, YN8 40, 39 YP9, YN9 43, 42 SCL 24 I SDA/SCL serial clock pin. Open drain. Always connect to a pull-up resistor. SDA 25 I/O SDA/SCL bidirectional serial data pin. Open drain. Always connect to a pull-up resistor. Configurable least significant bits (ADD[1:0]) of the SDA/SCL device address. The fixed ADD1, ADD0 37, 36 I most significant bits (ADD[6:2]) of the 7-bit device address are 11010. 7 Submit Documentation Feedback |
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