© 2005 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FIN24AC Rev. 1.0.3

11

Figure 11. Simplified Block Diagram for Unidirectional Serializer and Deserializer

Figure 11 shows basic operation when a pair of SerDes is configured in an unidirectional operation mode.

In Master Operation, the device:

1. Is configured as a serializer at power-up based on the

value of the DIRI signal.

2. Accepts CKREF_M word clock and generates a bit

clock with embedded word boundary. This bit clock is

sent to the slave device through the CKSO port.

3. Receives parallel data on the rising edge of

STROBE_M.

4. Generates and transmits serialized data on the

DS signals source synchronously with CKSO.

5. Generates an embedded word clock for each strobe

signal.

In Slave Operation, the device:

1. Is configured as a deserializer at power-up based on

the value of the DIRI signal.

2. Accepts an embedded word boundary bit clock on

CKSI.

3. Deserializes the DS data stream using the CKSI input

clock.

4. Writes parallel data onto the DP_S port and generates

the CKP_S. CKP_S is only generated when a valid

data word occurs.

Figure 12. Unidirectional Serializer and Deserializer

+

–

+

–

+

–

+

–

CKREF_M

CKSO

CKSI

CKP_S

DP[1:12]_S

Serializer

Control

BIT CK

Gen.

PLL

Master Device Operating as a Serializer

DIR = “1”

S2 = S1 = “0”

Slave Device Operating as a Deserializer

DIR = “0”

S2 = S1 = “0”

Deserializer

Control

Work CK

Gen

Serializer

Deserializer

DS

STROBE_M

DP[1:12]_M

CKREF

Note:

Data on serializer pins DP[21:22] is output on pins DP[23:24] of the deserializer.

Receiving

Unit

STROBE

DP[21:22]

CKSI

DS

DP[23:24]

DP[1:20]

CNTL[0:1]

DATA [0:19]

CNTL[0:1]

DATA [0:19]

DP[1:20]

DIRI

DIRI

S1

S2

S1

S2

CKSO

CKP

DS

FIN24AC

FIN24AC

Sending

Unit

REFCK