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FIN12AC Scheda tecnica(PDF) 8 Page - Fairchild Semiconductor |
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FIN12AC Scheda tecnica(HTML) 8 Page - Fairchild Semiconductor |
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8 / 24 page  © 2006 Fairchild Semiconductor Corporation www.fairchildsemi.com FIN12AC Rev. 1.1.0 8 Embedded Word Clock Operation The FIN12AC sends and receives serial data source synchronously with a bit clock. The bit clock has been modified to create a word boundary at the end of each data word. The word boundary has been implemented by skipping a low clock pulse. This appears in the serial clock stream as three consecutive bit times where signal CKSO remains HIGH. To implement this scheme, two extra data bits are required. During the word boundary phase, the data toggles either HIGH-then-LOW or LOW- then-HIGH, dependent upon the last bit of the actual data word. Table 2 provides some examples showing the actual data word and the data word with the word bound- ary bits added. Note that a 12-bit word is extended to 14 bits during serial transmission. Bit 13 and Bit 14 are defined with respect to Bit 12. Bit 13 is always the inver- sion of Bit 12 and Bit 14 is the same as Bit 12. This ensures that a “0” → “1” and a “1” → “0” transition always occurs during the embedded-word phase, where CKSO is HIGH. The serializer generates the word boundary data bits and the boundary clock condition and embeds them into the serial data stream. The deserializer looks for the end of the word boundary condition to capture and transfer the data to the parallel port. The deserializer only uses the embedded word boundary information to find and capture the data. These boundary bits are stripped prior to the word being sent out the parallel port. LVCMOS Data I/O The LVCMOS input buffers have a nominal threshold value equal to half VDDP. The input buffers are only operational when the device is operating as a serializer. When the device is operating as a deserializer, the inputs are gated off to conserve power. The LVCMOS 3-STATE output buffers are rated for a source / sink current of 2mA at 1.8V. The outputs are active when the DIRI signal is asserted LOW. When the DIRI signal is asserted HIGH, the bi-directional LVCMOS I/Os are in HIGH-Z state. Under purely capacitive load conditions, the output swings between GND and VDDP. Figure 8. LVCMOS I/O Differential I/O Circuitry The FIN12AC employs FSC proprietary CTL I/O technol- ogy. CTL is a low-power, low-EMI differential swing I/O technology. The CTL output driver generates a constant output source and sink current. The CTL input receiver senses the current difference and direction from the cor- responding output buffer to which it is connected. This differs from LVDS, which uses a constant current source output, but a voltage sense receiver. Like LVDS, an input source termination resistor is required to properly termi- nate the transmission line. The FIN12AC device incorpo- rates an internal termination resistor on the CKSI receiver and a gated internal termination resistor on the DS input receiver. The gated termination resistor ensures proper termination regardless of direction of data flow. The relatively greater sensitivity of the current sense receiver of CTL allows it to work at much lower current drive and a much lower voltage. During power-down mode, the differential inputs are dis- abled and powered down and the differential outputs are placed in a HIGH-Z state. CTL inputs have an inherent fail-safe capability that supports floating inputs. When the CKSI input pair of the serializer is unused, it can be left floating reliably. Alternately both of the inputs can be connected to ground. CTL inputs should never be con- nected to VDD. When the CKSO output of the deserial- izer is unused, it should be allowed to float. From Deserializer To Serializer From Control DP[n] Table 2. Word Boundary Data Bits 12-bit Data Words 12-bit Data Word with Word Boundary Hex Binary Hex Binary FFFh 1111 1111 1111b 2FFFh 10 1111 1111 1111b 555h 0101 01010 0101b 1555h 01 0101 0101 0101b xxxh 0xxx xxxx xxxxb 1xxxh 01 0xxx xxxx xxxxb xxxh 1xxx xxxx xxxxb 2xxxh 10 1xxx xxxx xxxxb |
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