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ISL54058 Scheda tecnica(PDF) 10 Page - Intersil Corporation

Il numero della parte ISL54058
Spiegazioni elettronici  Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer
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Produttore elettronici  INTERSIL [Intersil Corporation]
Homepage  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL54058 Scheda tecnica(HTML) 10 Page - Intersil Corporation

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10
FN6380.0
September 29, 2006
ISL54058
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 C
A
0.10 C
A1
SEATING PLANE
INDEX AREA
2
1
N
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
e
L1
NX L
2
1
0.10 M C A B
0.05 M C
5
NX b
(DATUM B)
(DATUM A)
PIN #1 ID
16X
3.00
1.40
2.20
0.40
0.50
0.20
0.40
0.20
0.90
1.40
1.80
LAND PATTERN
10
L16.2.6x1.8A
16 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTES
MIN
NOMINAL
MAX
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A3
0.127 REF
-
b
0.15
0.20
0.25
5
D
2.55
2.60
2.65
-
E
1.75
1.80
1.85
-
e
0.40 BSC
-
L
0.35
0.40
0.45
-
L1
0.45
0.50
0.55
-
N16
2
Nd
4
3
Ne
4
3
θ
0-
12
4
Rev. 4 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.


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