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ISL5416EVAL1 Scheda tecnica(PDF) 6 Page - Intersil Corporation |
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ISL5416EVAL1 Scheda tecnica(HTML) 6 Page - Intersil Corporation |
6 / 71 page 6 FSYNCA O Frame Synchronization output signal for bus Aout(15:0). FSYNCB O Frame Synchronization output signal for bus Bout(15:0). FSYNCC O Frame Synchronization output signal for bus Cout(15:0). FSYNCD O Frame Synchronization output signal for bus Dout(15:0). OEA I PULL UP Output three-state enable for Parallel Data Output bus A. Active low. OEB I PULL UP Output three-state enable for Parallel Data Output bus B. Active low. OEC I PULL UP Output three-state enable for Parallel Data Output bus C. Active low. OED I PULL UP Output three-state enable for Parallel Data Output bus D. Active low. MICROPROCESSOR INTERFACE P(15:0) I/O Microprocessor Interface Data bus. See Microprocessor Interface Section. P15 is the MSB. ADD(2:0) I Microprocessor Interface Address bus. ADD2 is the MSB. See Microprocessor Interface Section. WR or DSTRB I Microprocessor Interface Write or Data Strobe Signal. When the Microprocessor Interface Mode Control ( µP MODE) is low, data transfers (from P(15:0) to the internal write holding register) occur on the low to high transition of WR when CE is asserted (low). When the µP MODE control is high this input functions as a data strobe DSTRB control. In this mode with RD/WR low, data transfers (from P(15:0) to the internal write holding register) occur on the low to high transition of DSTRB. With RD/WR high the data from the address specified is placed on P(15:0) when DSTRB is low. See the Microprocessor Interface Section. RD or RD/WR I Microprocessor Interface Read or Read/Write Signal. When the Microprocessor Interface Mode Control ( µP MODE) is low, the data from the address specified is placed on P(15:0) when RD is asserted (low) and CE is asserted (low). When the µP MODE control is high this input functions as a Read/Write control input. Data is read from P(15:0) when RD/WR high or written to the appropriate register when low. See the Microprocessor Interface Section. µP MODE I PULL DOWN Microprocessor Interface Mode Control. This pin is used to select the Read/Write mode for the Microprocessor Interface. When 0, RD and WR, when 1, DSTROBE and RD/WR. When µP MODE is 0, the microprocessor interface consists of separate RD and WR strobes; when µP MODE is 1, the interface consists of a RD/WR control and a single data strobe. See the Microprocessor Interface Section. CE I Microprocessor Interface Chip Select. Active low. This pin has the same timing requirements as the address pins. Pin Descriptions (Continued) NAME TYPE INTERNAL PULL-UP/DOWN DESCRIPTION ISL5416 |
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