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ISL5571A Scheda tecnica(PDF) 8 Page - Intersil Corporation |
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ISL5571A Scheda tecnica(HTML) 8 Page - Intersil Corporation |
8 / 12 page 8 Idle / Talk State (LATCH = 0, INPUT = 0, TSD = 1 or Floating) In this state the Line Break switches (SW1 and SW2) are closed (on) and the Ring Return and Ring Access switches (SW3 and SW4) are open (off). The subscriber line circuit is either on-hook or off-hook: 1. In the on-hook condition, the SLIC is monitoring the Tip and Ring lines through the Line Break switches for an off- hook condition. This is called the Idle state. 2. In the off-hook condition, a telephone conversation between two or more parties is in progress or data is being transferred between modems. This is called the Talk state. The SLIC is providing DC power through the Line Break switches to the telephone handset for modulation. Modulated AC voice signals or data are traveling through the Line Break switches SW1 and SW2. Power Ringing State (LATCH = 0, INPUT = 1, TSD = 1 or Floating) In this state the Line Break switches (SW1 and SW2) are open (off) and the Ring Return and Ring Access switches (SW3 and SW4) are closed (on). For ring injected ringing as shown in Figure 1, a ring generator is connected to the phone through the Ring Access switch (SW4) and returned to ground through the Ring Return switch (SW3). All OFF State (LATCH = X, INPUT = X, TSD = 0) In this state both the Line Access switches (SW1 and SW2) and the Ring Return and Ring Access switches (SW3 and SW4) are open (off). The ISL5571A will enter the All Off state when the following conditions occur: 1. The TSD pin is used as a control input and is programmed to logic low. 2. The device has enter thermal shutdown due to a fault condition. (Thermal Shutdown is described in the Auxiliary Functions and Features section below.) 3. If VBAT rises above -10V or disappears. While in the All OFF state, communication and power ringing are inoperable because all the ISL5571A switches are open (off). Logic State Latch (LATCH = 1, TSD = 1 or floating, INPUT = 0 or 1) A Logic State Latch is Integrated into the ISL5571A, see Figure 2. If the LATCH control pin is high and the TSD pin is high or floating, the device will no longer respond to logic level changes at the INPUT pin. The state of the switches will be determined by the logic level of the INPUT pin at the time the LATCH pin transitions from logic low to logic high. The state of the switches at the time of this transition will be permanently held as long as the LATCH pin is high. When the LATCH pin is taken low the device will again be under the control of the INPUT pin and the switches will immediately go to the state specified by the logic level at the INPUT pin. (Note: The TSD pin overrides the LATCH pin and the INPUT pin. When the TSD pin is low the ISL5571A goes to the ALL OFF state regardless of the logic levels applied at the LATCH pin and the INPUT pin.) INPUT Pin The INPUT pin (pin 10) is the main logic input control pin. Reference Table 9 for logic state table. When the LATCH pin is low and the TSD pin is high or floating, you can toggle back and forth between the Idle / Talk state and the Power Ringing state by changing the logic level at the INPUT pin. This is the normal operating mode of the device. NOTE: If the LATCH pin is high, the INPUT pin is no longer active and the device will no longer respond to logic changes at the INPUT pin. The TSD pin overrides all other logic pins. If the TSD pin is low, the device will enter an All OFF state and will no longer respond to logic changes at the INPUT pin. Latch Pin The LATCH pin (pin 11) is the control for the Logic State Latch. Reference Table 9 for logic state table. When the LATCH pin is low, the latch is disabled and the state of the ISL5571A will be determined by the logic level applied at the other logic inputs. When the LATCH pin is high, the latch is active and the logic state of the switches at the time the LATCH pin went high will be latched. As long as the LATCH pin is held high the switches will not respond to logic changes at the INPUT control pin. LOGIC STATE LATCH INPUT 10 11 ISL5571A FIGURE 2. BLOCK DIAGRAM OF LOGIC CONTROL LOGIC SWITCHES TSD 8 CONTROL CIRCUITRY LATCH ISL5571A |
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