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74VCX16721MTD Scheda tecnica(PDF) 2 Page - Fairchild Semiconductor |
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74VCX16721MTD Scheda tecnica(HTML) 2 Page - Fairchild Semiconductor |
2 / 9 page www.fairchildsemi.com 2 Connection Diagram Truth Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial (HIGH or LOW, inputs may not float) Z = High Impedance O0 = Previous O0 before LOW-to-HIGH transition of Clock = LOW-to-HIGH transition Functional Description The VCX16721 contains twenty D-type flip-flops with 3-STATE standard outputs. The twenty flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-HIGH Clock (CLK) transition, when the Clock-Enable (CE) is LOW. The 3-STATE standard outputs are controlled by the Output- Enable (OE). When OE is HIGH, the standard outputs are in high impedance mode but this does not interfere with entering new data into the flip-flops. Logic Diagram CLK CE OE D0–D19 O0–O19 XX H X Z XH L X O0 LL L L LL H H L or H L L X O0 |
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