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74F675ASPC Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74F675ASPC Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 6 page © 2000 Fairchild Semiconductor Corporation DS009587 www.fairchildsemi.com April 1988 Revised October 2000 74F675A 16-Bit Serial-In, Serial/Parallel-Out Shift Register General Description The 74F675A contains a 16-bit serial in/serial out shift reg- ister and a 16-bit parallel out storage register. Separate serial input and output pins are provided for expansion to longer words. By means of a separate clock, the contents of the shift register are transferred to the storage register. The contents of the storage register can also be loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel loading. Features s Serial-to-parallel converter s 16-Bit serial I/O shift register s 16-Bit parallel out storage register s Recirculating parallel transfer s Expandable for longer words s Slim 24 lead package s 74F675A version prevents false clocking through CS or R/W inputs Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Order Number Package Number Package Description 74F675ASC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F675APC N24A 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600 Wide 74F675ASPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide |
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