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74AC646SC Scheda tecnica(PDF) 1 Page - Fairchild Semiconductor |
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74AC646SC Scheda tecnica(HTML) 1 Page - Fairchild Semiconductor |
1 / 9 page © 2000 Fairchild Semiconductor Corporation DS010132 www.fairchildsemi.com November 1988 Revised October 2000 74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs General Description The AC/ACT646 consist of registered bus transceiver cir- cuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin (CPAB or CPBA). The four fundamental data handling functions available are illustrated in Figures 1, 2, 3, and Figure 4. Features s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil dual-in-line package s Outputs source/sink 24 mA s ACT646 has TTL compatible inputs Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram Pin Descriptions FACT is a trademark of Fairchild Semiconductor Corporation. Order Number Package Number Package Description 74AC646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74AC646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 74ACT646SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74ACT646SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description A0–A7 Data Register A Inputs Data Register A Outputs B0–B7 Data Register B Inputs Data Register B Outputs CPAB, CPBA Clock Pulse Inputs SAB, SBA Transmit/Receive Inputs G Output Enable Input DIR Direction Control Input |
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