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AM49PDL127BH85IS Scheda tecnica(PDF) 4 Page - SPANSION |
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AM49PDL127BH85IS Scheda tecnica(HTML) 4 Page - SPANSION |
4 / 86 page 2 Am49PDL127BH/Am49PDL129BH December 16, 2003 ADV ANCE I N FO RMAT I O N HARDWARE FEATURES ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data ■ WP#/ACC (Write Protect/Acceleration) input —At V IL, hardware level protection for the first and last two 4K word sectors. —At V IH, allows removal of sector protection —At V HH, provides accelerated programming in a factory setting ■ Persistent Sector Protection — A command sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector — Sectors can be locked and unlocked in-system at V CC level ■ Password Sector Protection — A sophisticated sector protection method to lock combinations of individual sectors and sector groups to prevent program or erase operations within that sector using a user-defined 64-bit password pSRAM FEATURES ■ Power dissipation — Operating: 40 mA maximum — Standby: 70 µA maximum — Deep power-down standby: 5 µA ■ CE1s# and CE2ps Chip Select ■ Power down features using CE1s# and CE2ps ■ Data retention supply voltage: 2.7 to 3.3 volt ■ Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8) ■ 8-word page mode access |
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