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L6701TR Scheda tecnica(PDF) 6 Page - STMicroelectronics |
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L6701TR Scheda tecnica(HTML) 6 Page - STMicroelectronics |
6 / 44 page 2 Pins description and connection diagrams L6701 6/44 10 BOOT2 Channel 2 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE2 and provide necessary Bootstrap diode. A small series resistor upstream the boot diode helps in reducing Boot capacitor overcharge. 11 UGATE2 Channel 2 HS driver output. A small series resistors helps in reducing device-dissipated power. 12 PHASE2 Channel 2 HS driver return path. It must be connected to the HS2 MOSFET source and provides return path for the HS driver of channel 2. 13 BOOT3 Channel 3 HS driver supply. Connect through a capacitor (100nF typ.) to PHASE3 and provide necessary Bootstrap diode. A small series resistor upstream the boot diode helps in reducing Boot capacitor overcharge. 14 UGATE3 Channel 3 HS driver output. A small series resistors helps in reducing device-dissipated power. 15 PHASE3 Channel 3 HS driver return path. It must be connected to the HS3 MOSFET source and provides return path for the HS driver of channel 3. 16 SSEND / PGOOD SSEND - Intel VR10 Mode. Soft Start END Signal. Open Drain Output set free after SS has finished and pulled low when triggering any protection. Pull up to 5V (typ) or lower, if not used it can be left floating. PGOOD - Intel VR9 & AMD Hammer Mode. Open Drain Output set free after SS has finished and pulled low when VSEN is lower than the relative threshold. Pull up to 5V (typ) or lower, if not used it can be left floating. 17 DAC_SEL DAC SELection pin. It allows programming the DAC table for the regulation. Internally pulled-up to 5V. Short to GND to program VR9 DAC, leave floating to program K8 DAC while connect to GND through 82k Ω to program VR10 DAC. Information about the selected DAC is latched before the system start-up. See Section 7.1 for connections to enable CPU auto-detection. 18 OSC / EN / FAULT OSC: It allows programming the switching frequency FSW of each channel. Switching frequency can be increased according to the resistor connected from the pin vs. SGND with a gain of 4kHz/µA (see Section 14). Leaving the pin floating it programs a switching frequency of 100kHz per phase (300kHz on the load). EN: Forced low, the device stops operations with all MOSFETs OFF: all the protections are disabled except for Preliminary Over Voltage. When set low it resets the device from any latching condition. FAULT: The pin is forced high (5V) to signal an OVP / UVP FAULT: to recover from this condition, cycle VCC or the OSC pin. See Section 13 for details. Table 1. Pins description (continued) Pin n ° Name Function |
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