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SN74GTLP817PWR Scheda tecnica(PDF) 5 Page - Texas Instruments |
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SN74GTLP817PWR Scheda tecnica(HTML) 5 Page - Texas Instruments |
5 / 19 page www.ti.com Recommended Operating Conditions (1) (2) (3) (4) SN74GTLP817 GTLP-TO-LVTTL 1-TO-6 FANOUT DRIVER SCES285E – OCTOBER 1999 – REVISED APRIL 2005 MIN NOM MAX UNIT VCC Supply voltage 3.15 3.3 3.45 V GTL 1.14 1.2 1.26 VTT Termination voltage V GTLP 1.35 1.5 1.65 GTL 0.74 0.8 0.87 VREF Reference voltage V GTLP 0.87 1 1.1 BI VTT VI Input voltage V AI, OE VCC 5.5 BI VREF + 0.05 VIH High-level input voltage ERC VCC – 0.6 VCC 5.5 V AI, OE 2 BI VREF – 0.05 VIL Low-level input voltage ERC GND 0.6 V AI, OE 0.8 IIK Input clamp current –18 mA IOH High-level output current AO port –12 mA AO port 12 IOL Low-level output current mA BO port 50 ∆t/∆v Input transition rise or fall rate Outputs enabled 10 ns/V ∆t/∆V CC Power-up ramp rate 20 µs/V TA Operating free-air temperature –40 85 °C (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. (2) Normal connection sequence is GND first and VCC = 3.3 V, I/O, control inputs, VTT, VREF (any order) last. (3) VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded. (4) VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. 5 |
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